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CMOS tunnel FETs (TFETs) with vertical-tunnel-multiplication (VTM) were fabricated. VTM TFETs initiate band-to-band tunneling (BTBT) parallel to the gate electric field and effectively extend the tunnel area. Impact of the VTM was analyzed using a distributed-element circuit model, and the drain current multiplication by extended tunnel area was experimentally revealed for the first time.
In this work, we investigated the structure dependence of source and drain resistances on saturation currents for 17 nm bulk, SOI and Multi-Gate (MG) MOSFETs. An analytical saturation current model is proposed by considering with the higher order effects of source and drain resistances. For each structure, the saturation current (IDsat) were calculated by using the analytical current model. The reduction...
An analytical framework has been developed to describe the locking behavior of millimeter (mm) wave current-mode logic (CML) frequency divider. Unlike traditional analysis based on RC delay, the proposed model is established with injection-locking concept from analog perspective. Both analytical formulas and graphic interpretation are provided for design insights. The model has been validated by exhaustive...
The impact of contacts on device and circuit performance is becoming larger with technology scaling because of higher resistance as well as increased variability. Thus, techniques are needed for measurement, analysis, and modeling of variation in contacts, and for devices, interconnects, and circuits in general, in order to ensure robust circuit design. A test chip for characterizing contact plug...
An RF n-MOST model was developed based on PSP model, which is considered as one of standard surface potential based compact model for deep-submicron applications. The RF sub-circuit is presented after analyzing the structure and layout of a specific RF n-MOST, and the parasitic parameters extracted analytically. Validated in DC, AC small-signal, and large-signal analysis, it proves that an excellent...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
This paper presents the characteristics of bipolar transistors developed in a submicron CMOS technology. The collector is formed by high energy phosphorus implantation as is the PMOS well (``retrograde'' well). The performance of such devices is evaluated on ECL ring oscillators, and analysed via SPICE simulations. It is demonstrated that using the PMOS well as collector of the bipolar transistors,...
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