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FPGA is an efficient reconfigurable IC platform and is playing an increasingly important role in the electronics prototype implementation. With the rapid development of semiconductor technology and nano-technology over the last decade, FPGA has entered into a Giga-scale era. In this paper, the current status and future directions of Giga-scale FPGAs are presented. Specifically, the emerging technology-based...
An examination of large-scale stacking of 3D integrated ICs from a power-supply and thermal reliability perspective is presented. Noise characteristics and scaling issues related to through-silicon-via (TSV) size and pitch as well as other power-supply topology characteristics are included. Thermal simulations are carried out assuming the use of micro-fluidic heatsinks to provide cooling to systems...
With the feature size shrinking down to 65 nm and beyond, manufacturing process variation starts to significantly impact the device and interconnect electrical parameters, and therefore the performance of circuits. Back-end-of-line (BEOL) design for manufacturability concerns such as lithography variation and misalignment are more pronounced in the advanced technology node. Since SRAM cell always...
SRAM, the important memory component, has been widely used in design of digital and communication circuits. SRAM is also an effective vehicle for process development and qualification due to its complexity and high density in which an engineer is able to detect the process issues. Generally SRAM??s yield is used as an indicator of the semiconductor nodes yield. In this paper we present the analysis...
Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although...
In this paper we discuss some aspects of antennas in real designs in SOI technology, and show how the concepts manifest themselves in actual chips, where second-order effects such as resistance and the details of the processing sequence can play an important role. We also discuss the ramifications of a more recent technique which inserts bulk contacts into the SOI design, thereby imposing a bulk-like...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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