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The extent to which the 6T SRAM bit cell can be perpetuated through continued scaling is of enormous technological and economic importance. Understanding the growing limitations in lithography, design and process technology, coupled with the mechanisms which drive systematic mismatch, provides direction in identifying more optimum solutions. We propose an alternative, ultra-thin (UT) SRAM cell layout...
Accurate estimation of delays in Static Timing Analysis (STA) using Non Linear Delay Model (NLDM) based Look Up Table (LUT) is a major challenge in nanometer range VLSI circuits. Issues with NLDM based LUT are mostly due to the arbitrary choice of input signal transition time trin and load capacitance (Cl) and the large number of simulations to be performed for characterizing an entire standard cell...
AMD's two-core Bulldozer module implements the AMD x86-64 micro architecture in an 11-layer 32-nm SOI HKMG technology. The 40-instruction out of-order unified integer scheduler issues up to four operations per cycle and supports single-cycle wake-up of dependent operations. The 2.37mm2 integer execution unit supports single-cycle data bypass among four independent func tional units. Compared to previous...
The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and...
The quasi-adiabatic switching circuits reclaim part of the energy spent in the computation process and recycle the recovered energy for subsequent computations. The efficiency of such circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. These losses, in turn, are dependent on the operating frequency, the unclaimed charge trapped...
We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N--P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N--P transistor serves as load, respectively. Based on the measurement date of the N+-N--P transistor published, we draw the load line of the non-traditional...
Artificial bee colony (ABC) algorithm is a new population based metaheuristic approach inspired by intelligent foraging behavior of honeybee swarm. Since microelectronic circuit design deals with highly complicated nonlinear equations, obtaining optimal solution of these equations due to particular constraints in short time and acceptable error is of prime concern. Simpler structure and better result...
A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS technology is proposed in this paper. This inverter could be used as a fundamental block for designing other ternary basic logic gates. This circuit consists of only MOS transistors and capacitors without any area consuming resistors in its structure. Another great advantage of this design in comparison with the other...
In this paper, we report on the fabrication and characterization of a novel voltage-selectable (VS) nanowire (NW) CMOS technology suitable to extend the flexibility in circuit design and reconfigurable logic applications. Silicon NW-structures with Schottky-S/D-junctions on silicon-on-insulator (SOI) substrate are used to realize dopant-independent unipolar CMOS-like transistors. A selection of the...
Low-power circuits is quickly increasing their importance due to the high cost in design of cooling systems with complex chip packaging techniques, and also due to the low energy consumption requirement of portable devices powered by a limited battery capacity. This paper presents design of a low-power 32-bit adder that is a basic functional unit in most computational platforms. Its energy efficiency...
With the advance of nanometer technologies, the process variations play important roles in integrated circuit designs. The conventional corner value timing analysis becomes less effective and grossly conservative. Given a limited amount of measurement silicon data and without any distribution assumptions, this work develops a spatial correlation estimation methodology with the bootstrap resampling...
Charge recovery is a promising concept to design (cryptographic) VLSI circuits with low energy dissipation. However, unsatisfactory designs of proposed logic cells degrade its theoretical efficiency significantly both in its energy consumption and the resistance against differential power analysis attacks (DPA-attacks). Short circuit dissipation and non-adiabatic discharging of capacitance loads are...
Scan test is a powerful and popular test technique because it can control and observe the internal states of the circuit under test. However, scan path would be used to discover the internals of crypto hardware, which presents a significant security risk of information leakage. An interesting design-for-test technique by inserting inverters into the internal scan path to complicate the scan structure...
In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy applied only on critical parts of the circuit. The inherent property of the technique is that the improvement in the maximum frequency the circuit...
Since the introduction of energy harvesting and battery powered low- to mid-speed electronic circuits, supply voltages have been pushed to the physical limits of semiconductor devices for energy minimization and battery lifetime. Using the IBM 8RF-LM 0.13 ??m process and a modified library, an asynchronous ALU has shown to be capable of operating at 0.1 V. This paper presents the minimum energy analysis...
We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to hardware data correlation.
This paper describes ultra-low-power chip design using nano-scale electro-mechanical switches (NEMS) with graphene. This chip is attachable and detachable onto the top of other chips due to remarkable stickiness of carbon-nanotube interconnects. New 3D-IC can be thus constructed for reconfigurable system-on-chips. Furthermore, due to a floating gate built in NEMS, their logic performance is much superior...
Due to the increasing IC design complexity, Engineering Change Orders (ECOs) have become a necessary technique to resolve late-found functional and/or timing deficiencies. To fix timing violations, the principles of gate sizing and buffer insertion are commonly used in post-mask ECO. These techniques however may not be powerful enough, especially when spare cells are inserted in a way of striking...
Flexible electronics have attracted much attention since they enable promising applications such as low-cost RFID tags and e-paper. Thin-film transistors (TFTs) are considered as an ideal candidate to implement flexible electronics on low-cost substrates. Most TFT technologies, however, have only mono-type - either n- or p-type - devices and thus modern design technologies for silicon-based electronics...
In this paper, a new type of combinational logic circuit realization is presented. Logic values are implemented as sinusoidal signals. Sinusoidal signals of the same frequency are phase shifted by ?? to destructively interfere with each other, and represent the logic 0 and 1 values of Boolean Logic. These properties of sinusoids can be used to identify a signal without ambiguity. Thus, representing...
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