The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper compared the filling profile of electroplated Cu in through silicon via (TSV) with different aspect ratio at different current density. The experiment results indicated that bottom-up growth of Cu in TSV was obvious when the current density is 1 mA/cm2 and 3 mA/cm2. When the current density was 6 mA/cm2, the conformal growth of Cu was dominant. When the current density was 12 mA/cm2, the...
Pretreatments have a great effect on the through silicon via (TSV) copper electroplating filling process. In this study, we compared the wetting effect by observing cross-sectional images of samples pretreated with ultrasound and vacuuming method. And the electrochemical test was used to verify the effect of acid plating solution on the oxidation of the Cu seed layer. Without any pretreatment, vias...
In recent years, through wafer electrical connections have become important roles, which will be used in developing high-speed, compact 3D microelectronic devices in next generation. Although the electroplating copper is a well-established process, completely void-free electroplating in through silicon holes (TSH) with a high aspect ratio remains a big challenge. Naturally, local current distribution...
The fabrication of through-silicon vias (TSVs) is a major component in the development of three-dimensional (3D) integration technology and advanced 3D packaging approaches. The large diameter and length of TSVs, as compared to traditional interconnects, create some unique process challenges. Via plating and chemical-mechanical polishing (CMP) processes used in standard copper interconnect technology...
In this study, the effects of different influence factors on electroplating-based via-filling process were studied in a systematic manner. A through-silicon-via (TSV) chip was firstly designed, the chip size was 16 times 10 mm2 with the TSV interconnects. The via was in diameter of 50 mum and depth of 75 mum. The deep reactive ion etching (DRIE) technique was employed to fabricate the vias onto the...
Copper electrodeposition in acidic cupric methanesulfonate bath with organic additives is discussed in this paper. The influence of poly(ethylene glycol) (PEG) and bis-(3-sodiumsulfopropyl disulfide) (SPS) on copper deposition were studied by means of linear sweep voltammetry, cyclic voltammetry and chronoamperometry. These electrochemical analysises revealed a competition of PEG and SPS on electrode...
The through-silicon via is a key element in the development of 3D integration technology for new generations of advanced electronic systems. There are several challenges associated with filling these deep, relatively large diameter vias using standard copper electroplating processes, like those common in damascene technology. This paper will summarize a process development for copper electroplating...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.