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In this study, the effects of different influence factors on electroplating-based via-filling process were studied in a systematic manner. A through-silicon-via (TSV) chip was firstly designed, the chip size was 16 times 10 mm2 with the TSV interconnects. The via was in diameter of 50 mum and depth of 75 mum. The deep reactive ion etching (DRIE) technique was employed to fabricate the vias onto the...