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A set of low noise transimpedance amplifiers manufactured and characterized in CMOS and BiCMOS technologies is proposed in this work. Layout optimization, efficient modelling and bias point optimization are the techniques employed to reduce the input noise current density. The CMOS amplifiers were designed to work at 10 Gbps. The BiCMOS amplifiers, based on HBT transistors, can operate at bit rates...
We present the design and characterization of a broadband, low-noise transimpedance amplifier (TIA) with adjustable gain-peaking, implemented in 65-nm CMOS. The TIA exhibits 40-GHz bandwidth, 20-dB gain and consumes 107 mW power. An additional continuously-tunable 12-dB gain-peaking near 40 GHz is available through a simple yet effective tuning mechanism, consuming only 14% more power. The adjustable...
A 10-Gb/s transimpedance amplifier (TIA) for the parallel optical receiver module is realized in 0.18-μm CMOS technology. The proposed TIA employs a regulated cascode (RGC) input structure and adopts active inductor peaking and feedback techniques to enhance the bandwidth. Besides, a noise optimization is processed. The TIA provides a conversion gain of 50 dBΩ and 3-dB bandwith of 7 GHz. The measured...
A 10-Gb/s inductorless limiting amplifier for optic-fiber transmission system is designed and fabricated in a 0.18-μm CMOS technology. The whole circuit consists of an input buffer, three broadband gain stages, an output buffer for driving 50-Ω transmission lines and a DC offset cancellation circuit. By employing a third-order interleaving active feedback, the bandwidth of the proposed circuit can...
In this paper, a 10-Gb/s limiting amplifier (LA) was implemented in 0.18 mum CMOS. Modified active inductors and active feedback topology are employed to eliminate the trade-off among circuit bandwidth, power dissipation, and layout area, which is suitable for low cost applications. Based on the measurement results, the realized LA can operate up to 12-Gb/s with a 125 mVpp single-ended output through...
This paper describes the design of an optical receiver analog front end for a low power, high speed, chip-to-chip or board-to-board communication system. The circuit has been designed in 80 nm CMOS and consumes 2 mW with a 1-V supply. Using active inductors, a transimpedance gain of 62.5 dB-Omega, limiting amplifier gain of 15 dB, and overall bandwidth of 9 GHz was achieved. This work presents the...
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