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Interconnection networks with adaptive routing are susceptible to deadlock, which could lead to performance degradation or system failure. Detecting deadlocks at run-time is challenging because of their highly distributed characteristics. In this paper, we present a deadlock detection method that utilizes run-time Transitive Closure (TC) computation to discover the existence of deadlock-equivalence...
Irregular routing algorithms, as modified if fault tolerant algorithms, can be utilized by irregular networks. These algorithms conventionally use several virtual channels (VCs) to pass faults and oversized nodes. In this paper, a new wormhole-switched routing algorithm for irregular 2-D mesh interconnection Network-on-Chip is proposed, where no VC is used for routing. We also improve message passing...
Network-on-Chip (NoC) has emerged as a solution for communication framework for high-performance nanoscale architecture. One important aspect, in addition to deadlock-free routing, is low power consumption. In view of varied communication requirements, application specific SoC design is increasingly important. Customized NoC architectures are more suitable for a particular application, and do not...
ANoC (Asynchronous Network-on-Chip) has been developed to solve problems of large number of cores in SoC (System-on-Chip) by giving asynchronism to every core. This new architecture requires new Testing methods different from the existing SoC Test, and it freshly needs the test of router and routing networks. This paper first offers high-speed testing architecture that tests more than one routers...
Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace...
State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, system on chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated. However typical SoC communication infrastructure is based in standard buses and protocols which are difficult to...
Fault tolerant routing algorithms, are a key concern in on-chip communication. This paper examines fault tolerant communication algorithms for use in network-on-chip (NoC). We propose an improved wormhole-switched routing algorithm in 2-dimensional mesh based on f-cube3 algorithm to decrease message latency. The existing key concept is using numbers of virtual channels (VC) via a physical link. This...
We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in literature obtaining an optimized use of the channels of the network. This optimization allows to reduce the number of channels actually implemented on the chip while maintaining similar performances achieved by the two basic algorithms...
As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has greatly reduced router latency overheads and capitalized on available on-chip bandwidth, power constraints dominate interconnection network design. Recently research has proposed bufferless routers as a means to alleviate...
The design of efficient router represents a key issue for the success of the network-on-chip approach. This paper presents and evaluates novel router architecture suitable for networks-on-chip (NoC) design. This router offers lowest latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using fast parallel routing (FPR) arbitration that consists...
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