The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper discusses the implementation details and silicon result of a 1.6 GHz dual-core Cortex-A9 on a low power High-K Metal Gate 32 nm CMOS Bulk Process. The implementation is based on a fully synthesizable flow utilizing ARM Standard Cell and Memory IP. The completed design includes power gating and Dynamic Voltage Frequency Scaling capabilities for low static and dynamic power consumption and...
Bias Temperature Instability (BTI) causes significant threshold voltage shift in MOSFET using Hafnium-dioxide (HfO2) High-k dielectric material. Negative BTI and Positive BTI are two types of BTI effects observed in p-channel and n-channel MOSFET. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in nano-scale CMOS technology. Eight transistor (8T) and Ten transistor...
The next-generation enterprise Xeon® processor consists of 10 Westmere 32nm cores and a shared inclusive L3 cache (LLC) integrated on a monolith ic die, with link-based l/Os. This paper focuses on the innovations and circuit optimizations over the predecessor targeting idle power reduction, robust high-speed I/O links, and performance per watt improvements. The processor is implemented in 32nm CMOS...
In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM), read current, and standby power. The structures include SOI with ground plane in substrate (SOI-GPS),...
Leakage is a growing issue with the advancements of technologies. It is a predominant problem of on chip caches of microprocessors. The cache is a major portion of the microprocessor area. Further, the SRAM cell is a significant contributor of transistor leakage power. This paper analyses leakage-delay trade-off for increase of the transistor gate length in the on chip cache at 22nm, 32nm and 45nm...
SRAM 6T bitcell suffers many limitations in advanced technology nodes among which varaibility issues. Various alternatives have been experimented and the paper focuses the 5T portless bitcell. Read and write operations are operated by varying voltage conditions. The results in have been reviewed in CMOS 32nm and improvements have been provided. The bitcells are arranged in matrix to permit a current-mode...
This paper presents a configurable SRAM with 0.149 ??nf cell in 32 nm high-k metal-gate CMOS. Constant-negative-level write buffer adjusts bitline level automatically for configuration range of four to 512 cells/bitline, improving write margin at low voltage. Measurement results demonstrate that cell-failure-rate improves by two orders of magnitude at 0.5 V.
This paper proposes a new design for hardening a CMOS memory cell at the nano feature size of 32 nm. By separating the circuitry for the write and read operations, the static stability of the proposed cell configuration increases more than 4.4 times at typical process corner, respectively compared to previous designs. Simulation shows that by appropriately sizing the pull-down transistors, the proposed...
This paper presents a comparative study of two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 5 times larger tolerance to Vth and L mismatch...
CMOS technology has followed Moore's law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role...
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP)...
A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at Ioff=100 nA/mum, Vdd=1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of...
Floating body cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128 Mb floating body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single cell (1Cell/Bit) operation, are reviewed. Based on the experimental results,...
Active power, area, architecture, and timing constraints are the major factors in choosing SRAM-based memory organization in contemporary submicron SOCs. In this paper we add the effect of SRAM organization on leakage power as another major factor to consider in selecting a cache organization. Leakage power becomes an important factor for sub 100 nm process technology especially for SRAM-based memory...
A SRAM cell must meet stringent requirements for operation in the sub-micron/nano ranges. A nine transistor (9T) cell at a 32 nm feature size in CMOS is proposed to accomplish improvements in stability, power dissipation and performance compared with previous designs for low-power memory operation. Initially, this paper presents the optimal transistor sizing for this 9T SRAM cell considering stability,...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.