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A low-power multi-standard transceiver in CMOS 28 nm is presented. The transceiver can be configured to cover the range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver use a supply of 0.92 V. Transmitter uses a 3-tap Finite Impulse Response (FIR) filter and receiver uses a 3-tap analog FIR and 2-tap unrolled Decision Feedback Equalizer (DFE). The entire transceiver uses single level 0.92 V...
Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here we examine 25 Gb/s applications in the context of integrated transistor performance and demonstrate a 4λ×25 Gb/s reference design.
With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1–3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with...
A fully integrated 35GHz linearly Frequency Modulated Continuous Wave (FMCW) single-chip radar transceiver is successfully implemented in 65nm standard CMOS process. The single-chip transceiver is configured in one transmitter and two receivers and includes a wideband process-oriented optimized QVCO, a mm-Wave power amplifier, low noise amplifiers, low noise passive mixers, IF amplifiers as well as...
This paper presents three different low-power CMOS transceivers (TRx) for ZigBee, RFID and BLE designed at USTC. These TRx are compatible with three different IEEE standards. Firstly a highly integrated low-power 2.4GHz TRx with a low-IF receiver for IEEE 802.15.4 WPAN is briefed. Next, the TRx for Bluetooth Low Energy BLE 4.0 in standard 130nm CMOS is presented. Then, a low power UHF RFID Reader...
This paper reports a CMOS transceiver apt for integration with a digital microfluidic device, allowing electronic-automated sample management and measurement of micro-nuclear magnetic resonance (μNMR) signals inside a portable magnet. The transmitter (TX) employs an all-digital state control and a pulse sequence synthesizer to emit the exciting pulses for the samples. The receiver (RX) is led by a...
This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2Gb/s transmitter is designed with a low transmission power of −70dBm/MHz and a wide bandwidth of nearly 3GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a...
A low-power transceiver architecture for die-to-die applications is presented. The proposed transceiver employs CMOS logic-style circuits and a passive equalizer in the transmitter to reduce the power consumption. Single-ended signaling without a shared reference voltage is used to minimize the number of required signal traces and packaging bumps. A transceiver prototype is fabricated in 28 nm STM...
The MIPI RFFE slave interface circuit including Power-on-Reset (PoR), SCLK receiver and SDATA bidirectional transceiver has been implemented with a CMOS 250 nm process. Simulation results show that the designed circuit has SDATA output transition time (for rise and fall) of shorter than 3.3 ns at a full-speed rate of 26 MHz, which satisfies the timing requirement (< 6.5 ns) by the specification...
This brief presents a four-level pulse-amplitude modulation (4-PAM) transceiver for latency-sensitive network-on-chip (NoC) applications. The proposed source-synchronous PAM transceiver uses a novel encoder/decoder and dual-sampling technique that transmits and receives two data streams through a shared single-ended channel simultaneously. A conventional PAM transceiver for heterogeneous NoCs is sensitive...
A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10−12 while operating at 14Gb/s with 12dB channel loss.
This paper presents a 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. The parallel input to the transmitter is pre-coded at low frequencies, so that the pre-emphasis tap injects different currents into the output node of the transmitter based on different level changes of the output signal. The proposed pre-emphasis suppresses overshooting and lowers power consumption. The...
The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX)...
The IEEE 802.3an standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. The performance required from the analog front end (AFE) of a 10GBASE-T Ethernet transceiver strongly depends on the length of the cable connected to it. Maximum-length cables require the highest performance, and hence, determine the worst-case power dissipation of the transceiver...
A 16.8Gbps/channel single ended transceiver for SiP based DRAM interface on silicon carrier channel is presented. A transmitter, receiver, and channel are all included in a single package. On the transmitter, 1 tap FFEs are used in 4:1 MUX and in output driver. On the receiver, source follower based CTLEs and self Vref generator are used for obtaining effective single ended signaling on Si-carrier...
This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2–6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with...
This paper presents a low-power CMOS single-chip transceiver for sub-GHz wireless sensor network applications, which complies IEEE 802.15.4-2012 standard. It embodies RF transceiver section based on direct-conversion transmitter and low-IF receiver architecture. To validate its operation, the prototype is fabricated in 0.18um GF standard CMOS process. It shows +5dBm TX output power and −85dBm RX sensitivity...
Since the first OC-192 transceiver in CMOS was introduced in 2000, architecture and technology advancements have pushed wireline transceivers in CMOS to mainstream, even for OC-768 data rates. A diverse portfolio of multi-gigabit SerDes I/Os is now essential for large scale SOCs, not only for Networking but also Consumer applications. DSP-based transceivers with ADC frontends have forced a paradigm...
High-bandwidth wireline communication continues to be crucial for many electronic systems today. Numerous research efforts are dedicated to enhance speed, power efficiency, flexibility, and ease-of-use of these transceivers. This session includes some of the latest advances in this domain. The first transceiver paper employs a sub-sampling ring oscillator phase-locked loop (PLL) to obtain a large...
The speed of Ethernet over copper cables has steadily increased by a factor of 10,000 over the last four decades, from 1Mb/s in the earliest Ethernet implementations to 10Gb/s in recent systems. This paper describes the design considerations on all levels of the 10GBASE-T design hierarchy that form the basis for the implementation of highly power-efficient AFEs in full-duplex 10GBASE-T transceivers...
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