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This paper uses the Altera SDK for OpenCL (AOCL) High-Level Synthesis (HLS) tool to accelerate the computation of the SHA-1 hash function. Using FPGAs to increase throughput of this algorithm has been a popular topic in research. The work done thus far, focuses on HDL based design methodologies. The goal of this paper is to determine if the HLS implementation can compare in terms of speed to the HDL...
Smart City is becoming a commonly-used term to describe the concept of utilizing information and communication technologies (ICT) to enhance urban services and improve the quality of life for citizens. All communications should be fast and properly protected against unauthorized eavesdropping, interception, and modification. Therefore high speed and strong cryptography is required. Advanced Encryption...
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The paper first describes the design problem we have and then discusses our own HLS tool. The tool we developed has...
Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt-only AES-128 algorithm. Both designs integrate pipelining and iterative architectures in one design. This is achieved through applying the concept of partial loop unrolling where iterations and multistage pipelining are used to optimize...
This paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively...
Deoxyribonucleic Acid (DNA) sequence alignment is essentially a way of comparing two or more DNA sequences with aim to find regions of similarities among them. The Smith-Waterman (SW) algorithm is a local alignment algorithm which is able to identify mutation in DNA sequences. However, the aforementioned algorithm tends to be slower in computation of long DNA sequences. Over decades ago, Field Programmable...
The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure, high-throughput and area-efficient Field Programming Gate Arrays (FPGA) implementation of the Data...
The article presents the method for implementation and results of examination of the Pan-Tompkins algorithm using a specialized 4-core Azurite processor, based on MIPS-II instruction set. The algorithm is used to determine heart rate on the basis of ECG signals. Azurite is a Multiprocessor System-on-Chip featuring an analog and a digital part. The digital part has been implemented in a Xilinx Virtex-6...
We develop a new paradigm for designing fully streaming, area-efficient FPGA implementations of common building blocks for vision algorithm. By focusing on avoiding redundant computation we achieve a reduction of one to two orders of magnitude reduction in design area utilization as compared to previous implementations. We demonstrate that our design works in practice by building five 325 frames per...
Image scaling is a fundamental algorithm used in a large range of digital image applications. In this paper, we propose an efficient VLSI architecture for a novel edge-directed linear interpolation algorithm. Our VLSI design is implemented using high level synthesis (HLS) tool, which generates RTL modules from C/C++ functions. HLS provides significantly improved design productivity compared to the...
Second order Quadratic Programming (QP) solvers such as interior-point method (IPM) require the solution of a system of linear equations at every iteration and could be a factor limiting the implementation of IPM to miniaturized devices or embedded systems. In contrast, first order QP solvers such as alternating direction method of multipliers (ADMM) does not require the solution of a system of linear...
This paper presents the fast and area efficient CORDIC (Coordinate Rotation DIgital Computer)algorithm for sine and cosine wave generation. The concepts of pipelining and multiplexer based CORDIC algorithm is used todecrease the critical path delay and reducing the area respectively. A six stage CORDIC is implemented by two schemes followed by four methods, unrolled CORDIC and multiplexer based CORDIC...
In this paper, we propose a parameterized crypto co-processor based on Advanced Encryption Standard (AES). This parameterized AES module is combined with a 32-bit general purpose 5-stage pipelined MIPS processor. The AES module used in this paper is fully pipelined. The processor fetches an instruction from the instruction memory and sends it to the decode stage. If the instruction is the crypto instruction...
This paper tries to give a brief introduction on contemporary High-Level Synthesis (HLS). It covers following areas on HLS: design languages, main algorithms and flow, available commercial and academic tools, HLS application space, benefits of using HLS, and remaining challenges. The goals of this paper are to give reader an overview of HLS area, promote the adoption of HLS in the industry, and point...
Action recognition has been a research challenge in multimedia computing and machine vision. Recent advances in deep learning combined with stacked convolutional Independent Subspace Analysis (ISA) has achieved a better performance superior to all previously published results on several public available data sets. Unfortunately, one major issue in large-scale deployment of this new deep learning-based...
This paper presents an efficient floating point multiplier using Karatsuba algorithm. Digital signal processing algorithms and media applications use a large number of multiplications, which is both time and power consuming. We have used IEEE 754 format for binary representation of the floating point numbers. Verilog HDL is used to implement Karatsuba multiplication algorithm which is technology independent...
Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully...
NIST announced a public competition on Nov. 2, 2007 to develop a new cryptographic hash algorithm. Blake is one of the candidate among five finalist selected in round three of this competition. One of the major evaluation criteria of the candidate algorithm is efficient hardware implementation. In this paper compact area-efficient design of Blake-256 algorithm is implemented on FPGA. Horizontal Folding...
In this paper, we propose SHA-1 architectures to achieve high-throughput hardware implementations. Two techniques such as loop unfolding and pre-processing were used for high-speed SHA-1 core design. The system is made of four sub-modules to increase throughput. Xilinx Virtex-6 FPGA is used for implementation. Implemented SHA-1 module achieves a throughput of 7.35 Gbps, and its behavior has been verified...
A new FPGA-based implementation scheme of the AES-128 (Advanced Encryption Standard, with 128-bit key) encryption algorithm is proposed in this paper. For maintaining the speed of encryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 128-bit plaintext and the 128-bit initial key, as well as the 128-bit...
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