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The S-Box operation in the Advanced Encryption Standard has a long history of research in tailored and optimised hardware designs. While Canright's design based on tower-field decomposition has long been a benchmark design for low area, designs based on linear-feedback structures achieve lower area and power consumption at the price of additional clock cycles. We combine both approaches to get a design...
The cyclic redundancy check (CRC) is a popular error detection code (EDC) used in many digital transmission and storage protocols. Most existing digit-serial hardware CRC computation architectures are based on one of the two well-known bit-serial CRC linear feedback shift register (LFSR) architectures. In this paper, we present and investigate a generalized CRC formulation that incorporates negative...
In this paper the design of programmable bit-serial Reed-Solomon encoders is considered using the traditional Berlekamp multiplier. It is suggested that there are certain advantages to be gained by deriving the generator polynomial of the code using combinational logic, or equivalently using look-up tables, rather than using an iterative LFSR based approach. The use of the recently proposed Berlekamp-like...
In this paper, a view point of classification of linear codes based on algebraic structure and Local Cyclic Codes is presented. Linear codes are divided into two types (structural and non-structural); almost all these codes are used widely in practice. Local Cyclic Codes are described in relation with other linear codes. These codes are constructed on decompositions of polynomial ring according to...
This paper proposes a structure for a digital coder, optimizing the multiplication circuit area that leads to a substantial gain in the main circuit surface and helps future decoding. The work describes the functioning process, the technical design and tests the coder's main functions. The evolution of RS coding and the growing pallet of application domains are also briefly covered.
This paper describes and compares two scrambler architectures developed and implemented in an advanced field programmable gate array (FPGA), with applications in 100 Gbit/s optical transport network (OTN) systems.
This paper focuses on the design and implementation of MMC intelligent controller. MMC intelligent controller can be easily applied to any design and can be operated easily through the MCU software. It provides a variety of interfaces between MMC and MCU.
LFSR based PN Sequence Generator technique is used for various cryptography applications and for designing encoder, decoder in different communication channel. It is more important to test and verify by implementing on any hardware for getting better efficient result. As FPGAs is used to implement any logical function for faster prototype development, it is necessary to implement the existing design...
The main purpose of this paper is to study the FPGA implementation of two 16 bit PN sequence generator namely Linear Feedback Shift Register (LFSR) and Blum-Blum-Shub (BBS). We have used FPGA to explain how FPGA's ease the hardware implementation part of communication systems. The logic of PN Sequence Generator presented here can be changed any time by changing the seed in LFSR or by changing the...
The following article provides a description of an application of the pseudo random signals generators, based on dynamic linear feedback shift registers, used in the DSSS spread spectrum communication. Due the changes of generator's feedback loop in time, the length of pseudo random sequence is much longer. An implementation of the dynamic linear feedback shift register generator (DLFSR) in VHDL language...
It is very important to obtain very good low-rate codes with increased speed, due to its importance in modern communication systems. This paper proposes an effective method to achieve very-low-rate convolutional codes, with minimum generator polynomials and higher speed.
In this paper a flexible, high-throughput, low-complexity additive white gaussian noise (AWGN) channel generator is presented. The proposed generator employs a Mersenne-Twister to generate a long random number uniformly distributed sequence and a Box-Muller transformation implementation to derive gaussian noise samples. Emphasis is given on developing a high-throughput approximation unit for the elementary...
This paper presents a hardware design for a scalable, high throughput, configurable LFSR. High throughput is achieved by producing L consecutive outputs per clock cycle with a clock cycle period that, for practical cases, increases only logarithmically with the block size L and the length of the register N. Flexibility is ensured by offering full reconfigurability of the generator polynomial within...
AES has been widely used in cryptographic modules of many hardware devices such as communication chips or broadcasting receiver chips. AES may be theoretically safe; however, cryptographic device with it is vulnerable to side channel attacks such as differential power attacks due to leakage information. In this paper, we propose countermeasure techniques for AES hardware chips with S-box hiding using...
Providing a suitable key establishment scheme in wireless sensor networks is challenging due to all the characteristics of these networks, such as limitations of power, computation capability and storage resources. Several key management schemes were proposed, but most of them are not resilient to nodes capture. In order to improve the resilience to nodes compromising, in this paper we propose an...
The Alternating Step(r, s) Generator, ASG(r, s), is a clock-controlled sequence generator which is recently proposed by A. Kanso. It consists of three registers of length l, m and n bits. The first register controls the clocking of the two others. The two other registers are clocked r times (or not clocked) (resp. s times or not clocked) depending on the clock-control bit in the first register. The...
Quadratic permutation polynomial (QPP) interleaver has the advantage of contention-free for parallel memory access and has been adopted in the 3GPP LTE for turbo coding. Conventional implementations of the QPP interleaver based on the look-up table or on-line calculation usually result in large circuit area or higher clock rate for parallel turbo decoding. In this paper, an architecture design of...
The new radio broadcasting standards as Digital Radio Mondiale (DRM) and HD Radio impose new demands on AM transmitters. Nowadays, two modulating designs dominate over the AM transmitter market - Pulse Width Modulation (PWM) technology and digital technology. In both cases, it is profitable to implement the modulator in all-digital form, which enables to use powerful DSP algorithms. This paper presents...
Design of key generator is the core process in stream cipher. This paper discusses the security of the LFSR and nonlinear combining functions as two core components of key generator. The models studied in this paper include linear shift register sequence, Geffe sequence, shrinking feedback sequence and widespread to the general nonlinear combining sequence. Improvement advice is proposed for cryptographist...
ECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level.
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