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This paper describes a set of state-of-the-art race logic synthesis technologies for multithreaded/multi-core HDL (hardware description language) and ESL (electronic system level) simulators, such as V2Sim™ [1]. The new technologies aid V2Sim™ to automatically eliminate race logic in large-scale System-on-Chip (SoC) circuits [2.3], so that V2Sim™ multithreaded simulation results will be the same as...
The increasing complexity in the design of protocol based sequential digital systems such as USB3.0 and PCI express (PCIe), is leading to an increased time to market constraint. This paper introduces a UML based visual design approach to address this increased complexity in the design of IP as well as System-on-Chips (SoC). A hardware development method for USB3.0 device using the Unified Modeling...
This paper presents a methodology for modeling and simulation of analog/mixed-signal systems using Verilog-AMS. Through this approach, it becomes more efficient and convenient to model analog, digital and mixed-signal design. Moreover, it is also a good solution for analog/mixed-signal verification because simulation time will be greatly decreased in this way. The applied methodology brings together...
The importance of System-On-Chip (SoC) validation continues to grow with the increase of design size. How to measure the completeness and quality of validation approach? An innovative domain coverage metric is proposed in this paper. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that point on or near the boundary is most sensitive to domain...
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditions rare. However, recent design methodologies do not always satisfy these assumptions. For instance, third-party IP blocks used in a system-on-chip are often over-designed for the requirements at hand. By focusing only on the...
As the rapid development of semiconductor technology, more and more processor cores and large reusable components have been integrated on a single silicon die. And the rapid increase of requirement from applications is leading to the exploration of SOC.On-chip-bus is a key part of SOC.A SystemC-based Transaction Level Modeling of on-chip-bus is introduced in this paper. As an example, the DVB-C is...
Currently, Transaction Level Modeling (TLM) is being used in the industry to solve a variety of practical problems during the design and deployment of electronic systems. TLM and SystemC gain popularity partly due to their simulation capabilities. However, formal models associated to SystemC designs and TLM descriptions are less developed. This paper describes how to translate SystemC modules defined...
The main focus of this work is the functional verification of radio frequency systems on chip (RF SoCs). Different modeling approaches, like baseband modeling, analog modeling and event driven modeling, and their applications for verification are discussed. The possibilities and problems to use the Hierarchy Editor (HED) to switch between different modeling approaches on the fly in the top level schematic...
This paper presents our approach of the radio interface problematic for wireless sensor network. We introduce the WSN context and constraints associated. We propose an IR-UWB solution and illustrate why it could be a viable solution for WSN. A high level modelling and simulation platform for IR-UWB radio interface is proposed on Matlab. It allows us to determine according to BER versus Eb/N0 criteria...
We consider a high performance software/hardware implementation of fault and fault -free simulation methods, and linting-technology for early design stage verification as well. Application of these technologies allows significant increasing simulation performance in comparison with software tools, and reducing design time of very high scale integrated circuits for 20-30%.
A time-domain event-driven VHDL simulation technique for modeling a multigigahertz radio-frequency digitally controlled oscillator (DCO) for wireless applications is presented. The model includes various phase noise mechanisms including flicker (1/f noise), thermal wander, jitter and flat electronic quantization noise due to the digital control using time-domain equations. The noise models are implemented...
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