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This paper investigates the peculiarities of the coding transformant bit view taking into account the observed regularities of binary structures based on the positional structural-weight (PSW) coding. It is proved that the technology of the PSW coding has two mechanisms for compensation of the influence of structural characteristics of a transformant binary format (the quantity of bits of compressed...
This article describes a high-speed technology for description and solving logical problems, using the Boolean graphs of associative tables, by means of hardware implementation of parallel synthesis and analysis of algebraic, graph and tabular structures of predicate relations for obtaining deterministic multivalued result in n-dimensional discrete space. The problems of creating a theory of brain-like...
This article describes a high-speed technology for description and solving logical problems, using the Boolean graphs of associative tables, by means of hardware implementation of parallel synthesis and analysis of algebraic, graph and tabular structures of predicate relations for obtaining deterministic multivalued result in n-dimensional discrete space. The problems of creating a theory of brain-like...
The base elements of the architectural keeping of heights of relief of image are expounded. Grounded, that the architectural keeping provides: decline of time of forming and treatment of videoinformation, presented on the basis of isotopic description of relief of image and architectural keeping; potential possibility for forming of compact presentation of videoinformation without the loss of information...
We consider a high performance software/hardware implementation of fault and fault -free simulation methods, and linting-technology for early design stage verification as well. Application of these technologies allows significant increasing simulation performance in comparison with software tools, and reducing design time of very high scale integrated circuits for 20-30%.
Method of digital device testability analysis, which represented on the system level (VHDL description) as oriented graph for verification and test synthesis tasks simplification for fault coverage improving on the given test patterns is offered. Method is based on the topological analysis of oriented graph and his further modification by separation of testing and functional procedures for testability...
A high performance fault simulation method based on the superposition procedure is offered. It is oriented on large digital designs processing. Evaluation of RT and gate level design description is proposed in this work. The data structure and program are developed for algorithms' realization of the proposed method and integration with automatic test pattern generation systems.
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