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In this paper we present an example of a DISPLAY-CTRL IP component verification in an SCE-MI based emulation platform. The basic parts of this platform are some transactors. Their task is communication between the testbench written in the high level language SystemC (software side) and the IP component, placing in FPGA on an emulation board (hardware side) through an SCE-MI infrastructure. Using the...
The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of ARTiSAN Studio®...
The flow of universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, hardware part and software part of a design are described with SystemVerilog and SystemC, respectively after hardware/software partitioning. The functional interaction...
In this paper a partly unified hardware/software design flow is presented. It uses System C as system level design language and postpones the partitioning decision to a lower abstraction level by using a realization independent functional model. Especially the partitioning of data flow dominant tasks between hardware and software is simplified with this approach. Additionally, by using a C-based design...
Today, designs of electronic systems are driven by application-specific embedded systems and system-on-chip (SoC). Designing these systems with conventional RTL-centric approach takes extremely long simulation cycles and painful verification process. The trend now is to describe these systems at a higher level of design abstraction. In this paper, we present a SystemC-based hardware/software (HW/SW)...
This paper presents the design of a network master device for the multifunction vehicle bus. An analysis of the specifications for this bus administrator reveals that the functional design can be arranged in 14 operational blocks and in a special memory for communication data known as the traffic store. System-on-a-chip strategies have been adopted in order to cope with this great complexity. The...
The design of embedded systems is rapidly changed during the last decade. It is possible to identify two main factors that are involved in this process: HW/WS codesign and dynamic reconfigurable architecture. This work aims at introducing an innovative methodology that allows to easily implement on an FPGA a system specification, taking as input its high-level description, such as C or SystemC, and...
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework comprising of well-defined communication protocols and synthesizable communication wrappers, the process of refining the TLM specification of a HW/SW system to its synthesizable implementation can be systematically automated. We...
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