The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The performance of a wireless system depends on the wireless channel as well as the algorithms used in the transceiver pipelines. Because physical phenomena affect transceiver pipelines in difficult to predict ways, detailed simulation of the entire transceiver system is needed to evaluate even a single processing block. Further, some protocol validations require simulation of rare events (say, 1...
Packet classification involving multiple fields is used in the area of network intrusion detection, as well as to provide quality of service and value-added network services. With the ever-increasing growth of the Internet and packet transfer rates, the number of rules needed to be handled simultaneously in support of these services has also increased. Field-Programmable Gate Arrays (FPGAs) provide...
The EnDat2.2 interface protocol developed by HEIDENHAIN company lately with its high-speed, bi-directional and pure digital features can meet the requirement of rapid responses, dramatically cut down the overall system's cost and greatly reduce the space requirements of the system's installation. Therefore, it is widely used in Numerical control system like CNC system and photoelectric encoder. China's...
This paper presents the hardware-software co-design platform based on FPGA developed for fast prototyping of embedded systems using hardware modules that can be easily connected and “driver” modules that can manage I/O devices and sensors basic behavior. Having this framework, adding of a new I/O peripheral needs only design and synthesis of an application specific VHDL or software module. Using neural...
Reconfigurable network hardware makes it easier to experiment with and prototype high-speed networking systems. However, these devices are still relatively hard to program; for example, requiring users to develop in Verilog or VHDL. Further, these devices are commonly designed to work with software on a host computer, requiring the co-development of these hardware and software components. We address...
The use of switched Ethernet for safe real-time communication still suffers from undesired phenomena, such as blocking caused by long non-preemptive frames, lack of protection against errors in the time domain, couplings across virtual LANs and priority levels via internal switch shared resources. Recently, a few solutions were proposed to cope with such phenomena. One such solution is based on an...
Multi-cipher and multi-mode cryptosystems are widely used for hardware acceleration in modern security protocols. In a session of communication, these protocols can only use an algorithm along with its operation mode. The switching of cipher algorithms and operation modes can occur between sessions of communication. This paper introduces a multi-cipher cryptosystem (MCC) which enables a cryptosystem...
The dynamic reconfiguration technique based on FPGA (field-programmable gate array) can improve the resource utilization. The dynamic reconfiguration principles and methods are discussed. A remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet PHY (physical layer transceiver) is proposed. The hardware of system is designed with Xilinx Virtex-IIXC2V30P FPGA that embeds...
This paper presented fieldbus SOPC-based FSB (fast serial bus) controller using FPGA technology for CNC application, which used H/S(hardware/software) codesign method. This controller completed control of AL (application layer), DLL(data link layer) and PL(physical layer). In the controller, CAN-compatible hardware designed by VHDL handled with DLL and PL of FSB, while software run in soft processor...
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-to-chip interconnect which is particularly used in AMDs novel Opteron processor series. As it is an open protocol, a broad application range exists ranging from southbridge chips over closely coupled accelerators to add in cards. Its...
This work describes the evaluation of a hardware/software co-design flow based on the synchronous language Esterel. The paper starts with a short introduction into Esterel and tackles available tools. The focus of this work is an examination of the design flow concerning the practical applicability, based on case studies and related work. Advantages and draw-backs of the design flow are discussed...
This paper presents the development and test of the standard IEC-60870-5 application layer protocol over TCP/IP for a remote terminal unit (RTU) based on open hardware and software. The RTU hardware is an embedded system, a SoC-type design using FPGA that has been programmed with the open core LEO/ with Linux operating system running over it, so both the and IOS are open source. For prototyping the...
Wireless sensor networks require the design of highly energy-efficient and yet flexible sensor nodes. The hardware flexibility required for dynamic adaptation is traditionally achieved with software based processors or field programmable gate arrays (FPGAs), both of which come with significant energy, area and performance costs when compared to application-specific integrated circuits (ASICs). In...
Many FPGAs are served as network devices today. The ability of networked reconfiguration of such devices can enable the control and upgrading of them from a long distance. Previous researches on networked reconfiguration focused on hardware implementation of network protocols, neglecting there configuration integrity and security. This paper analyzed potential threats to reconfiguration integrity...
The dynamically reconfigurable MAC processor is an innovative architecture specialized for the wireless MAC layer, and aimed at consumer hand-held devices. It is a software/hardware partitioned platform where the microprocessor uses a reconfigurable hardware co-processor to delegate critical tasks. This allows the microprocessor to handle fast and complex MAC protocols while clocking at relatively...
Optical network unit (ONU) and optical line terminal (OLT) are two basic device elements in an Ethernet passive optical network (EPON). To support an optical multi-point network, the multi-point control protocol (MPCP) is being standardized in the IEEE 802.3ah task force (Ethernet in the first mile -EFM) by defining a multi-point MAC control sublayer as an extension of the existing MAC control sublayer...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.