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In this paper, hardware optimization of the preprocessing and software implementation of the processing blocks of a computer-aided semen analysis (CASA) system are proposed, which is also implemented on an FPGA and ARM device as a working prototype. The software implementation of the track initialization, track maintenance, data validation and classification blocks of the processing part are implemented...
In this paper, hardware optimization of the preprocessing part of a computer aided semen analysis (CASA) system is proposed, which is also implemented on an FPGA device as a working prototype. A real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping...
This paper presents a complete system to detect scratches in rolls of photo paper. The idea is to use a group of white LED to illuminate the picture and highlight the scratches only. The system mainly consists of a camera to obtain images from the paper and an Altera DE2-70 FPGA Board to process those images. We can show that observing the scratches by applying specific filters on the acquired image...
A kind of image processing with a low power dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3 implemented with 65 nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3...
Small satellites have captured the imagination worldwide of satellite designer due to its exciting technological and economic possibilities. Thus, pico satellites team of research group on intelligent machines laboratory, is developing ERPSat-1, ENIS REGIM pico satellite 1, the first pico satellite of the engineering school of Sfax, Tunisia. ERPSat-1 has three basic missions such as ground station...
ArMen is a parallel machine in which each node is coupled to an FPGA ring. The underlying idea is to complement an MIMD architecture with global coprocessors providing extra control and processing properties. The use of regular hardware patterns such as cellular automata or pipelines allows high level definitions of the coprocessors. The results are fast prototyping possibilities for specific applications...
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