The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, we propose globally asynchronous locally synchronous (GALS) pipelined MAC using Baugh Wooley multiplier with complex numbers for FFT applications. The primary objective of the design is on low power implementation of MAC unit. Fully synchronous and GALS pipelined MAC unit are implemented using same FPGA and logic cells for fair comparison of results. Fully synchronous MAC unit dissipates...
Star trackers measure the attitude of a spacecraft by matching the stars captured by the camera and those stored in the onboard database, whose directions are already known. The information (i.e., location and brightness) on the stars in the captured image must be correctly and timely provided for star recognition. This process is called star centroid extraction. The hardware implementation of the...
In this paper we present a system that we made for acquisition and processing of data on multiple channels (8 in total) and transmitting the remote results through the Ethernet interface. The solution chosen by us involves the system implementing in FPGA where any processes running in parallel can be described — the acquisition processes from the AD sensors and possibly data processing processes....
Some computationally complex problems require complex solutions in terms of number of processors and diversity of computation methods. Metabolic systems are naturally capable of solving complex problems; they are mathematically modelled with hundreds of differential equations. In order to understand those metabolisms or simply replicate their functions in engineering problems, we need a large network...
Implementation of embedded systems-on-chip on modern field programmable gate arrays (FPGAs) chip is doable due to its large density. Architecture of multilevel computing focusing on its embedded processor is suggested in our project. The architecture design of embedded processor presents the challenges and opportunities that stem from the task coarse granularity and the large number of input and output...
The Advanced Telecommunications Computing Architecture (ATCA) standard describes a powerful and efficient platform. With multiple integrated solutions like redundancies and intelligent control mechanisms this technology is characterized with reliability estimated at the level of 99.99999 percent. These features make the standard perfect for use in projects like the Free Electron Laser in Hamburg (FLASH)...
In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics...
Small form factor (SFF) software defined radio (SDR) platform is used to implement an experimental cognitive radio for first responders. The system was demonstrated in the 2007 Software Defined Radio technical conference and product exhibition, and is selected for presentation in the demonstrations and experimentation track in the IEEE DySPAN 2008. Different processing tasks are divided between a...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
SpaceWire is a network for connecting instruments and other equipment into the payload data-handling system onboard a spacecraft. It provides high-speed (2-200 Mbits/s), bi-directional communications over point-to-point links and network capabilities using routing switches. One of the key features of SpaceWire is its simplicity resulting in low gate count implementations enabling SpaceWire interfaces...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.