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We propose a novel design flow for mismatch and process variation aware optimization of nanoscale CMOS active pixel sensor (APS) arrays. As a case study, an 8 times 8 APS array is designed using the proposed methodology for 32 nm CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR) and capture time (delay) have been measured. The baseline results show a power...
This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology,...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
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