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A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing...
Design of contemporary digital circuits has great need of power reduction. The reasons are owing to portable applications and CMOS Deep-Sub-Micron technology. Finite state machines (FSM) play an important role in these circuits. The partitioning of an FSM into several sub-FSMs is a technique widely used in the reduction of energy consumption. An interesting style for activating and deactivating sub-FSMs...
Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68% and static power consumption of 15% are achieved.
The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism...
Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs)...
Artificial bee colony (ABC) algorithm is a new population based metaheuristic approach inspired by intelligent foraging behavior of honeybee swarm. Since microelectronic circuit design deals with highly complicated nonlinear equations, obtaining optimal solution of these equations due to particular constraints in short time and acceptable error is of prime concern. Simpler structure and better result...
A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS technology is proposed in this paper. This inverter could be used as a fundamental block for designing other ternary basic logic gates. This circuit consists of only MOS transistors and capacitors without any area consuming resistors in its structure. Another great advantage of this design in comparison with the other...
This paper presents a clock and data recovery (CDR) circuit that supports dual data rates of 5.4Gbps and 3.24Gbps for DisplayPort v1.2 sink device. The quarter-rate linear PD in the proposed CDR reduces jitter by enhancing the up and down pulse width. A charge pump (CP) is designed to compensate the different up and down pulse width of the PD and to reduce the current mismatch and power consumption...
Energy efficiency and idle power consumption are becoming important parameters in the design of embedded systems that are realized with nanometer-scale CMOS devices. In nanometer-scale CMOS, Excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. To address energy efficiency and idle power consumption, we present a novel Complementary Nano-Electro-Mechanical...
Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit...
The design of high speed, compact and low power priority encoder circuits using static CMOS gates is presented. The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation. For an 8-bit priority encoder design the proposed approach shows 77.1% power dissipation, 63.6% transistor count and 36% delay improvement. The improvement increases...
As CMOS technology is reaching the nanometer scale, transient and intermittent faults occurrence in logic circuits, which implies a reliability degradation, can no longer be neglected. This paper deals with reliability evaluation which is a critical parameter in circuit design. The proposed method is scalable, iterative and accelerates the reliability analysis.
In this paper, a novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization of nano-CMOS circuits. For demonstration of the effectiveness of the flow, a 45nm single-ended 7-transistor SRAM is used as example circuit. The SRAM cell is subjected to a dual-VTh assignment based on a novel statistical Design of Experiments-Integer...
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a second gate, enabling the design of generalized logic gates with a high expressive power, i.e., the ability to implement more functions with fewer physical resources. Reported circuit design techniques using generalized logic gates...
Based on divide-by-4/5 divider, a divide-by-32/33 dual modulus prescaler is designed with characteristics of high operating frequency, low supply voltage and low power dissipation. The circuit is simulated by the simulator, Eldo under the TSMC 90 nm low power CMOS process. The simulated results show that the highest operating frequency is up to 6 GHz, and drains only 0.99 mA from a 1.2 V supply voltage.
The PMOS/NMOS width ratio (??) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional CMOS logic design style. In this paper we propose a simulation-based method applied to CMOS inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1, 4 and 8 cells of similar type are present. The appropriate...
We focus in this work on threshold logic gates (TLQ) implemented using double-gate (DG) MOSFETs. The proposed TLQ's can be programmed dynamically via secondary (back) gate using the same bias conditions as the primary (front) gate. Moreover, they can realize universal threshold logic functions, which comprise Boolean operations as a subset.
This paper presents a new cell family designed to perform reconfigurable operations in nanometric systems. Using new properties given by emerging devices, we can create cells based on various improvement objectives, such as increasing density or elementary device functionality. Therefore, a reconfigurable logic cell using high-density emerging technology is able to achieve an area improvement of over...
Reducing leakage dissipation is becoming more and more important in low-power design. The dynamic energy dissipation reduction of adiabatic circuits using power-gating schemes has been introduced. In order to reduce leakage losses of the adiabatic circuits using power-gating schemes under deep submicron process, this paper proposes a MTCMOS (Multi-Threshold CMOS) power-gating scheme for adiabatic...
The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus...
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