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We present the development of a high-k first n-channel InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs) and the effect of annealing on the source/drain (S/D) sheet resistance (Rs) and the high-k gate oxide. Test structures based on the transfer length method (TLM) were used as part of a design of experiment (DOE) to optimize the S/D implant activation process. The optimized process...
High-performance implant-free In0.53Ga0.47As-channel MOSFETs grown on GaAs substrates by Metalorganic Chemical Vapor Deposition (MOCVD) are demonstrated. Atomic-layer-deposited (ALD) Al2O3 was used as gate dielectric on top of a δ-doped In0.53Ga0.47As/In0.51Al0.49As metamorphic heterojunction structures grown on GaAs substrates. A 1-μm gate-length MOSFET with 15nm Al2O3 shows a maximum drain current...
We report the integration of silane and ammonia (SiH4 + NH3) surface passivation technology to realize high-quality gate stack on a high-mobility In0.53Ga0.47As compound semiconductor. Vacuum anneal at 520??C desorbs the native oxide while preserving the surface morphology and material composition of In0.53Ga0.47As. By incorporating SiH4 + NH3 passivation, a thin silicon oxynitride (SiOxNy) interfacial...
InGaAs has been extensively studied as a potential channel material for sub-22nm gate length VLSI MOSFETs because of its low electron effective mass (m ) hence high electron velocity (v). At sub-22 nm gate lengths, a maximum 1 nm EOT dielectric and 5 nm thick channel with strong vertical confinement are required for high subthreshold slope and acceptably low drain induced barrier lowering (DIBL)....
A scalable, self-aligned In0.53Ga0.47As MOSFET process was developed and enhancement mode device operation was demonstrated. The 0.7 mum Lg device shows a maximum drive current of 0.14 mA/mum at Vgs=4.0 V and Vds=2.5 V. The devices have almost an order of magnitude larger drive current than our previously reported MOSFETs. The channel layer was 5 nm thick InGaAs with InAlAs bottom barrier for vertical...
We report the first demonstration of strained III-V n-MOSFETs with lattice-mismatched source/drain (S/D) stressors. Lateral tensile strain was induced by In0.4Ga0.6As S/D on the In0.53Ga0.47As channel. In-situ doping was incorporated as well for series resistance reduction. We also integrated SiH4+NH3 passivation for reduction of interface state density on In0.53Ga0.47As for the first time.
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