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This work demonstrates a fully integrated 24 GHz CMOS receiver for high gain and wireless sensor network. The receiver incorporates a low noise amplifier, double-balanced mixer and an active balun for single to differential. This mixer designs with active load to decrease power dissipation. To increase mixer gain, an inductor is added to eliminate parasitic capacitances at the load of input transistor...
This paper presents the design and simulation of an inductive degeneration low noise amplifier (LNA) for impulsionel radio ultra wide band receiver for biomedical implant. Several techniques was used in this study to improve the LNA features for the [1,5]GHz frequency band. The most important are the use of the diode connected load, the degeneration source and the cascode design. A fully integrated...
In this paper, a distributed amplifier (DA) with a feed forward path is presented to reduce noise effects of input matching termination at the output. The proposed active termination (AT) technique also improves the amplifier gain without increasing its power consumption. To validate the introduced method, a four-stage wideband actively terminated DA (ATDA) is designed in a 0.18μm CMOS technology...
This paper presents the design and simulation of High gain Source degenerated Cascode LNA for Wi-max and W-CDMA applications at 3.5GHz. The design uses an enhanced cascade topology to attain improved forward gain and noise figure. Th is design includes lumped elements like inductor, capacitor and resistors to design input and output matching networks. The targeted narrow-band gain, impedance matching...
This paper presents the design of an inductor-less low noise amplifier (LNA) using high tunable and novel active inductor in 0.18um CMOS technology. A high tunable active inductor is used instead of spiral inductor. A common source cascode amplifier with RC feedback is used in the LNA circuit topology. Input and output impedance matching is implemented by using two stages source follower circuit to...
One of the important components of a receiver is the low noise amplifier (LNA). The challenges of LNA design include ability to achieve high gain, low noise figure and better linearity at low power consumption within the required frequency. In this paper, our design is based on Impulse Response (IR) Ultra-Wideband (UWB) transceiver operating at 3.1–4.6GHz. Hence the LNA designed has been optimized...
A low-noise amplifier (LNA) integrated circuit (IC) has been designed and implemented on a 0.13um RF CMOS process technology. The LNA was designed to resonate at 450MHz frequency. This paper presents the design methodology and compares the simulated and measurement results of the cascode LNA with inductive degeneration. There were expected mismatch between simulation and measurement data, thus some...
This paper describes a wide band/high dynamic range receiver implemented in a 0.18-μm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The system demonstration is a single conversion architecture with RF input at X-Band and IF output at S-Band. The receiver yielded 20–21.5 dB conversion gain, 5.6–6 dB noise figure, and 16.7 dBm OIP3 across a 600-MHz instantaneous bandwidth at S-Band operation.
This paper presents the design of a 30 GHz low noise amplifier in a 130 nm CMOS technology. The amplifier is based on a cascode topology. The circuit uses autotransformers in the input and output matching networks. This design approach eliminates the necessity of the use of source degeneration and allows obtaining an ultra compact LNA. The amplifier presents a forward gain (S21) of 7.4 dB at 30 GHz...
In this paper, we proposed a low noise amplifier (LNA) for ultra wideband (UWB) application using TSMC 0.18μm CMOS technology. To satisfy the wide input matching, LC high-pass filter matching network is utilized in the first stage. To obtain the low power characteristic, folded-cascode with current reused technique is utilized in the second stage. The designed UWB LNA has the voltage gain of 17.6...
In this paper, the amplifier path consisting of the low-noise amplifier (LNA) and programmable-gain amplifier (PGA) is designed. For lower input-referred noise power, the active input impedance termination should be indispensable. The novel circuit is proposed for high-performance LNA. The PGA is designed to cover the operating range of 48dB. The analog front-end is designed and verified in a 0.18-μm...
This paper presents a low-noise active balun with broadband phase-correction. The proposed phase-correction structure is independent of operation frequency, and effectively suppresses phase deviation of active balun at millimeter-wave (MMW) band. Within the low noise current-reuse pre-amplifier, this active balun circuit can be employed as low-noise amplifier as well. This circuit is fabricated in...
A 2.4GHz receiver front-end with on-chip balun implemented with 0.13um CMOS technology is presented in this paper. Based on direct-conversion architecture, the front-end comprises a two-stage LNA (low noise amplifier) with optimized on-chip transformer and quadrature passive mixer. The gm-boosting technique is employed in 1st stage of LNA to achieve low noise and low current simultaneously. In 2nd...
A dual-band 2.1GHz/5.2GHz low noise amplifier (LNA) which can operate at mobile band of 2.1GHz and WLAN band of 5.2GHz frequency is proposed. Input matching, noise matching and narrow-band amplifying are achieved at two frequency bands by adopting a switched inductive output load and a positive-negative feedback circuit. The proposed LNA is implemented in SMIC 0.13 μm CMOS technology with a supply...
A high linearity variable gain low noise amplifier (VGLNA) used for WCDMA receiver is presented. Power constrained simultaneous noise and input matching (PCSNIM) technique is adopted to design the inductive source degenerated LNA. To improve the dynamic range of the receiver, capacitive divider and current steering technique are adopted to implement the three gain modes. The chip was manufactured...
This paper presents a dual-path noise-cancelling (DPNC) LNA, which is designed for low power wireless sensor network (WSN) applications and operates at 2.4GHz band. The proposed DPNC LNA can effectively cancel internal circuit noise while consuming less power by gm-boosted technique. The measured voltage gain and NF are 22dB and 3.7dB, respectively. IIP3 is +8dBm and consumes 1.2mW with a 1.0V single...
One band switchable low noise amplifier (LNA) is designed for wideband applications. The proposed band switchable LNA has two switchable bands. The design consists of a input matching circuit, two cascode common-source amplifiers and an output buffer for measurement. The proposed LNA is designed with two switching capacitors as loading that use NMOS to make high quality factor. The proposed LNA gives...
A 6-9GHz Ultra-Wideband (UWB) CMOS differential low noise amplifier (LNA) for the high frequency band of China UWB standard is proposed. Compared with the conventional band-pass filter wideband input matching, the number of inductors is saved by the high-pass filter topology presented. The virtual ground of the differential LNA formed at the `tail' removes the sensitivity to parasitic ground inductance...
A low noise amplifier (LNA) is proposed for a 35GHz ultra-wideband (UWB) system. The combination of a common-gate (CG) input stage and a common-source (CS) input cascode stage is exploited with a modified form of noise cancellation. The proposed LNA is implemented in a 0.18μm CMOS technology and achieves a power gain of 18dB, an average noise figure of 3.3dB, and better than -11dB of input/output...
This paper presents a 0.9GHz-10GHz Ultra Wideband Low Noise Amplifier (LNA) designed for software-defined-radios (SDR). Capacitive cross coupling (CCC) is used at both input stage and cascade stage for wideband input impedance matching and small noise figure (NF). A combination of inductor peaking load and series inductor between the cascade stages of LNA is employed for a flat gain and enhanced input...
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