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This paper reports the development of a single-mask CMOS-compatible process for creating three dimensional buried channels (3DBCT). The structures are formed in silicon using isotropic SF6 plasma etching in a deep reactive ion etcher and are then sealed by depositing a low-stress dielectric material using low-temperature plasma enhance chemical vapor deposition. Utilizing reactive ion etch lag, this...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
A new type of precision thinned bonded silicon wafer is evaluated for thin film CMOS/SOI applications. SOI wafers with silicon film thickness variations of less than ??2.5 nm are available with choice of substrate doping and buried oxide thickness. CMOS devices fabricated on these wafers have the same carrier mobilities as comparable bulk silicon MOSFETs.
Dry etching techniques are used for monolithic integration of a mirco system consisting of a pressure sensor, integrated optics and VLSI CMOS circuits. The sensor is etched from the front side of the wafer and with the support of TEOS-spikes the membrane is deposited by PECVD technique.
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