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This paper investigates the substitution of CMOS or near-threshold CMOS with Charge Recovery Logic (CRL) in applications where energy is thermally harvested. By doing so, it is possible to eliminate the bulky DC/DC stage needed to provide the supply voltage for CMOS operation. Instead, a simple LC-tank oscillator is used to generate a power-clock suitable for CRL operation. Simulation results of a...
This paper proposes a low power, low voltage Truly Random Number Generator (TRNG) for EPC Gen2 RFID tag. According to the special requirements of Gen2 tag, design considerations and tradeoffs among chip area, power consumption and randomicity are presented. The proposed TRNG is composed of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers...
A low power on-chip reference clock generator consisting of subthreshold MOSFET circuits is proposed. It uses a simple frequency-locked loop technique with no inductor, quartz resonator, or MEMS oscillator. Theoretical analyses and a SPICE simulation with 0.35-mum CMOS parameters showed that the clock frequency could be controlled in the frequency range of 10-1000 kHz. When operated at 170 kHz, the...
In this paper, a low-power signal processing front-end and PIE decoder for use in UHF RFID passive transponders is presented. By merging with the decoder, the clock generator does not need to drive a large loading capacitor. Therefore, its power consumption can be greatly reduced. In addition, the ring oscillator of the generator was designed for low sensitivity to supply voltage variation and low...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Standby power of a 32k ?? 8 pseudo-static RAM has been reduced to 60uA using an expanded internal refresh interval, a reduced oscillating frequency by a back bias generator, and other power saving circuits.
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