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Microelectronic integrated circuits experience nonuniform high temperatures during normal operation. Thermal expansion mismatch among the different materials comprising the device lead to a large tensile stress after high temperature cycles. Voiding and open-circuit failure from cracking of interconnects are often observed during isothermal aging and thermal fatigue tests with or without electric...
Chemical vapor deposited (CVD) Ruthenium liners and DirectSeedTM (DS) copper were used with advanced Electrofill processes to provide lower resistance wiring compared to results using CVD Ru and conventional physical vapor deposited (PVD) Cu seed for back end of line (BEOL) structures. Different annealing temperatures and simulated BEOL thermal stress builds were used to show the difference in resistance...
Stress migration (SM) and electromigration (EM) are key reliability concerns for advanced metallization in nanoscale CMOS technologies. In this paper, the interaction between these two mechanisms is studied in dual-damascene Cu/low-k interconnects. It is found that these mechanisms are not independent; EM failure time could be strongly affected by the presence of residual stress induced by SM, causing...
The ever increasing scaling down of IC leads to ever more current density in interconnects. As a consequence, electromigration (EM) becomes a concern in interconnect reliability. In order to face this problem and allow more current density in design, one can take advantage of the Blech effect. Many investigations have proposed extraction methods, behaviors or values for the threshold jLc product but...
The effects of dielectric slots on Cu/Low-k interconnects reliability were studied. Dielectric slots were proven to be effective in suppressing stress-induced void failure but their impact on EM reliability was found to be minimal. Physical failure analysis and finite element simulations were used to explain the possible mechanisms associated to the different effects of dielectric slots on Cu/low-k...
Upstream electromigration (EM) study was performed on different multiple via structures with different Cu line dimensions. EM performance was found to be dependent on both via layout and Cu line dimension. Failure analysis showed different EM failure modes and diffusion paths on these structures with their different grain morphology. Finite element analysis is applied to find out the current density...
Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface...
The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80 nm integrated in a k = 2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other...
We investigate the critical current density for electromigration failure, jc, as a function of voiding failure mode for Cu dual damascene vias. We demonstrate experimentally the variation of (jL) product with via failure mode showing that it is not possible to characterize vias by a single (jL). We suggest that, in general, jc for failure is determined by the sum of void nucleation and growth components,...
Electromigration results are described for a dual damascene structure with copper metallization and a low-k dielectric material. The failure times follow a bimodal lognormal behavior with early and late failures. Moreover, there is evidence of a threshold failure time such that each failure mode is represented by a 3-parameter lognormal distribution. It is found that the threshold failure time scales...
A reliability evaluation of a 300-mm-compatible 3DI process is presented. The structure has tungsten through-Si-vias (TSVs), a hybrid Cu/adhesive bonding interface, and a post Si-thinning Cu BEOL. The interface bonding strength, deep thermal cycles test, temperature and humidity test, and ambient permeation oxidation all show favorable results, indicating the suitability of this technology for VLSI...
We have conducted stress-induced voiding (SIV) experiments on Cu/low-k interconnect with different geometries of via structures and upper metal cap layers to evaluate their reliability impact. We showed the cap layer of upper metal had strong effect on the SIV performance. The degrees of such SIV degradations varied with different via structure geometries. A 3D Finite Element Analysis (FEA) is applied...
Asymmetrical Cu interconnect structure, where one end of the metal-2 (M2) test line is connected to M1 while the opposite end is connected to M3, was subjected to very long periods of bipolar pulsed current (i.e. 2, 16 and 48 hours) in this study. The median-time-to-failure (t50) of the samples was found to depend on the direction of electron current in the first half-period, and t50 of samples that...
Electromigration under bidirectional current is studied on dual damascene copper interconnects for the 65 nm node. Physical analyses confirm void location a both ends of the line and copper transport over long distance. Resistance evolution was studied and correlated to void healing/growth kinetics. Finally, we show the interest of bidirectional tests to study multimodal failure mode.
Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types...
We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 - 0.42 squarem. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance...
We investigate electromigration void morphologies, associated resistance increases and failure distributions for down-stream electron flow of Cu dual damascene via structures. We show that void formation occurs below the traditionally defined critical current density, and we develop a model to accurately predict via failure distributions as a function of current density.
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