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Cellular Automata with Random Memory (CARM), which has been recently introduced, is a time-delay discrete time system such that delay is a random variable. Delay in discrete time systems can be easily generated from a random delay characteristics of wires and transistors in programmable logic devices. Therefore implementation of CARM model is not required any special hardware. In this paper, a new...
The vision of a software defined radio (SDR) is to implement in different software systems of communications using the same hardware platform. An advanced SDR system consists of two fundamental components: a programmable RF component and another reconfigurable FPGA-based component in charge of performing high-speed signal processing. Since the sampling rate of the ADC and DAC converters is generally...
In recent years, FPGA is becoming popular among researchers and big companies who apply FPGA to high performance computing and deep learning as it has advantages over GPU in many aspects like performance, flexible programmability, cost, etc. However, the key stage placement in FPGA design flow remains to be one of the most challenging problem as the designs become larger and more complex. In this...
Field programmable gate arrays (FPGAs) have been adopted in various fields, due to the design flexibility and customizability. Different applications have different requirements in performance, hardware resources and cost, leading to demands of diverse FPGA architectures. Delay is an important metric to evaluate different alternatives during FPGA architecture development. The existing analytical delay...
A pair of 32 bit Gaussian Random Numbers (GRaNs) is generated. Box Muller (BM) transformation is widely used for generation of high quality Gaussian Random Numbers in hardware. The BM transformation is a direct method to convert random numbers into a Gaussian random numbers. For the generation of uniform random number skip-ahead linear feedback shift register (SA-LFSR) is used which is given as input...
Performance of adders has a tremendous impact on system-level functionality especially in signal processing applications. Carry Select Adder (CSLA) is one such adder which is proved to be a high speed version among other conventional adders. This paper presents a novel architecture for SQRT-CSLA with modified ripple carry adder chain. The pivotal feature of the proposed architecture is that the final-sum...
In this paper step by step procedure for the construction of a high speed FIR filter is developed based on the concept of Vedic mathematics as well as modified Booth Wallace technique. MAC units made with both these techniques give comparative results. The objective of this paper is to find the better technique suited to the application of MAC as a filter.
Active noise control (ANC) is an efficient technique to deal with low frequency noise that is difficult to be abated by noise barrier or sound absorbing material. Many successful ANC systems have adopted the feedforward filtered-x least mean squares (FxLMS) algorithm to reduce machinery noise. The noise canceling headset is another well known example, where the feedback control structure is favorable...
We introduce a novel methodology for identifying the worst-case test vector for flash-based FPGA devices exposed to total ionizing dose based on cell-level fault models of delay failures.
We have proposed a new security platform: physical unclonable function (PUF) matching using programmable delay lines (PDL). Our platform inherits good security properties of standard PUFs, such as low energy, low delay, and unclonability. However, standard PUF-based security protocols induce high computational resources of at least one involved party. To resolve this issue, we take advantage of PDL...
In this paper, we analyze through analytical and experimental means the impact of different SEU induced mechanisms modifying delays in I/O blocks of SRAM-based FPGAs. We propose simple RC delay models for these mechanisms. Our results, obtained through HSPICE simulations and experimental SEU emulation, show the relevance of these delay models. They also show that these mechanisms differ from the ones...
Regenerative ranging (RR) is a turn-around noise free method for measuring the distance of an interplanetary spacecraft from the Earth. Weighted (υ=2, υ=4) and balanced Tausworthe codes (T2B, T4B) are used as pseudo-noise (PN) ranging sequences. In this paper we show how to implement on Field Programmable Gate Arrays (FPGAs) a digital regenerative ranging transceiver that, on the spacecraft, receives...
There are many engineering simulations and scientific computing applications where large linear system of equations are to be solved. With the generous development in scientific computing the use of large linear system of equations also increases. There are many solvers for solving these equations. Jacobi is one of the important solvers for solving linear system of equations. Jacobi method is more...
The evolution of wireless technology to its fourth generation has improved exponentially from its predecessor. On the other hand, this improvement requires a higher level of complexity and computation to process the signal. In this paper, we propose an architecture for 4G LTE's time domain baseband signal processor. To improve the computation time so that it meets the real-time specification, we propose...
Embedded systems (ES) based on field programmable gate arrays (FPGAs) enhance the overall computational capability and relieve computational load. The lack on design and implementation methods for specific control functions in hardware limits the application of complex control techniques. Therefore, a design methodology approach is showed in the current work. Fuzzy, LQR, and PI control systems are...
In this document we implemented several digital and filtering techniques in real time using Xilinx Zynq-7010 FPGA To achieve this we use a high level programming language like NI LabView to generate the VHDL that will be recorded in the hardware. We expose the mathematic characteristics of each one of the effects and the impact in the processing of the audio signal. We also compare with those we obtained...
A Hardware Trojan is a malicious hardware modification of an integrated circuit. It could be inserted at different design steps but also during the process fabrication of the target. Due to the damages that can be caused, detection of these alterations has become a major concern. In this paper, we propose a new resilient method to detect Hardware Trojan based on path delay measurements. First, an...
This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate, and interpolation...
Dedicated Short-Range Communication (DSRC) technology is developed for use in vehicle-to-vehicle (V2V) and vehicle-to-roadside/infrastructure (V2I) communications. It uses Orthogonal Frequency Division Multiplexing (OFDM) as constrained by IEEE 802.11p standard. In this standard, the OFDM uses 64 sub-carriers. This paper presents the design on Field Programmable Gate Array (FPGA) Xilinx Spartan-3E...
Molecular dynamics (MD) is a large-scale, communication-intensive problem that has been the subject of high-performance computing research and acceleration for years. Not surprisingly, the most success in accelerating MD comes from specialized systems such as the Anton machine. Our goal is to design a reconfigurable system that can accelerate MD while also being amenable to other communication-intensive...
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