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Efficient synchronization is a key concern in an embedded many-core system-on-chip (SoC). The use of atomic read-modify-write instructions combined with cache coherency as synchronization primitive is not always an option for shared-memory SoCs due to the lack of suitable IP. Furthermore, there are doubts about the scalability of hardware cache coherency protocols. Existing distributed locks for NUMA...
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
This paper deals with the management of a SoC-based current controller using an efficient Real-Time Operating System (RTOS). To accelerate the services of this operating system, a Real-Time Unit (RTU) was developed in VHDL and associated to the RTOS. It consists in hardware operating system that moves the scheduling and communication process from software RTOS to hardware. Thus, a significant acceleration...
In this paper we present the power optimization of a GNSS, Bluetooth, FM radio combo SoC for smartphones and tablet devices. The optimization ranges from architectural level, clock management level and RTL level. The techniques of power state and power control, clock gating, clock distribution, operand isolation and logic grouping have been tailored to the specific needs of wireless combo SoC. The...
This paper describes our third generation multicore processor that exhibits a high level of integration [1]. The current design doubles the number of cores, triples the frequency and more than quadruples total memory bandwidth over [1]. It contains 700M transistors and has been fabricated in a 65nm process technology, with 10 layers of copper interconnect and C4 bumps. It contains 32 MIPS cores, 4MB...
A new methodology for formal system verification of System-on-Chip (SoC) designs is proposed. It does not only ensure correctness of the system-level models but also of the concrete implementation at the Register-Transfer-Level (RTL). For each SoC module at the RTL an abstract description is obtained by path predicate abstraction. Since this leads to time-abstract system models the main challenge...
With a significant increase in the design complexity of cores and associated communication among them, post-silicon validation has become a demanding task in System on Chips (SoCs) design. To ensure that final products are fault-free and ready for market, the post-silicon validation goal is to catch bugs and pinpoint the root causes of errors that could escape from pre-silicon verification tools....
Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establishing coherence and consistency for different types of shared memory by hardware means. Also support for...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
Today's embedded systems are considering cache as inherent part of their design. Unfortunately, cache memory behavior heavily depends on the past references which model a large execution history and makes WCET analysis impractical. This paper presents a novel prefetch memory mechanism that simplifies the prediction of cache hits/misses because the memory access times are independent of the execution...
Virtual platform simulation is an essential technique for early-stage system-level design space exploration and embedded software development. In order to explore the hardware behavior and verify the embedded software, simulation speed and accuracy are the two most critical factors. However, given the increasing complexity of the Multi-Processor System-on-Chip (MPSoC) designs, even the state-of-the-art...
Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using...
Parallelized shared variable applications running on multi-core Network-on-Chips (NoCs) require efficient support for synchronization, since communication is on the critical path of system performance and contended synchronization requests may cause large performance penalty. In this paper, we propose a dedicated hardware module for synchronization management. This module is called Synchronization...
This paper explores a dynamic buffer allocation technique to guide a distributed synchronization architecture to support efficient synchronization on multi-core Network-on-Chips (NoCs). The synchronization architecture features two physical buffers to be able to concurrently queue and handle synchronization requests issued by the local processor and remote processors via the on-chip network. Using...
Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the long-term verification of industrial embedded systems, forcing the designer to implement ad-hoc verification solutions. This contribution presents a suitable solution for long-term verification of FPGA-based designs consisting on a verification core that uses the Picoblaze microcontroller, dedicated logic...
This paper proposes a packet-based verification platform with serial link interface for emulating the hardware of the heterogeneous IPs before tape out. With the serial link interface Serializer/Deserializer (SerDes) added between IPs, significant amount of pin counts can be reduced in the platform. An adapter is inserted between IP and SerDes to convert parallel bus into packets and handle the handshaking...
Energy consumption is a major issue in the design of embedded systems that are battery-driven. At the architectural level energy savings can be realized by a diversity of mechanisms. This paper presents the energy-savings mechanisms that are part of the time-triggered architecture (TTA). The paper starts with a general section on energy dissipation in VSLI circuits and an outline of the architectural...
Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(System-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented...
A SoC typically integrates multiple peripheral IPs. Each one of these IP's has its own interfaces and integration requirements. The test benches designed for these IP's are different and require independent porting of test-cases on the SoC, thereby extending the test time. Also, practically there may not exist any use case that requires all these IPs at the same time. In this paper we propose a novel...
This paper presents CODESL, a SystemC-based hardware-software co-design and co-simulation framework for embedded systems based on system-on-chip (SoC). This modelling platform, which works at Electronic System Level (ESL), enables early system functionality verification, as well as algorithm exploration before the final implementation prototype is available. It can validate the behaviour for both...
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