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This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole...
We describe the design and development of an optoelectronic lock-in amplifier (LIA) for optical sensing and spectroscopy applications. The prototype amplifier is fabricated using Taiwan Semiconductor Manufacturing Co. complementary metal-oxide semiconductor 0.35-μm technology and uses a phototransistor array (total active area is 400 μm × 640μm) to convert the incident optical signals into electrical...
A TSMC 0.35 um CMOS 2P4M process PLL (phase-locked loop) for ISM band applications is proposed. The PLL, with a crossed-coupled pMOS ring-oscillator VCO, is realized without using any inductor. Measurement results show that at the supply voltage of 3.3 V and the lowest reference frequency of 25 MHz, the locking range is from 1.8 GHz to 3.29 GHz, locking time is less than 3 us and the phase noise is...
A surface acoustic wave (SAW) device is used in this work as the sensing element for a chemical sensor that will be embedded in a wireless sensor node. The SAW device is intended to detect the concentration of gaseous mercury in the environment. Two behavioral models of the SAW device have been studied. The microelectronics front-end architecture has been designed at transistor level in a 0.35 mum...
The phenomena of charge injection, clock feedthrough and charge sharing in charge pump are analyzed. A novel structure of charge pump for high-speed phase-locked loop is presented. The charge pump is designed with the Chartered 0.35 mum CMOS technology, and simulated with Eldo which is the analog circuits simulation tool of Mentor Graphics. Under 3.3 V DC supply voltage, the power consumption is 0...
Phase-locked loops (PLLs) are used to implement a variety of timing related functions such as frequency synthesis, clock and data recovery, and clock de-skewing. Any jitter or phase noise in the output of the PLL used in these applications generally degrades the performance margins of the system in which it resides and so is of great concern to the designers of such systems. Jitter and phase noise...
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