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The reason that existing models have underestimated the parasitic resistance of nano-scale MOSFET biased at low gate voltage was discussed. Then an improved resistance model was proposed. Finally, the influences of several technical parameters on the parasitic resistance were analyzed through numerical simulation, and some directions and measures might be taken to reduce the parasitic resistance.
The potential distribution for the channel depletion layer of fully depleted SOI LDMOS was obtained by using quasi- two-dimensional approach, and an analytical threshold voltage model was established. The accuracy of the model is verified by comparison with the results of 2-D semiconductor device simulator MEDICI. From this model, we can find how the channel length, channel doping concentration, the...
The phenomena of charge injection, clock feedthrough and charge sharing in charge pump are analyzed. A novel structure of charge pump for high-speed phase-locked loop is presented. The charge pump is designed with the Chartered 0.35 mum CMOS technology, and simulated with Eldo which is the analog circuits simulation tool of Mentor Graphics. Under 3.3 V DC supply voltage, the power consumption is 0...
A 36 MHz intermediate frequency amplifier (IFAMP) is designed using Chartered 0.35 um CMOS technology. The nonlinear characteristic of IFAMP is analyzed, and the technology of leading compensation and miller capacitance compensation is adopted. The circuit simulation tool is ELDORF which provided by Mentor Graphics. Simulation results show that IFAMP has greater than 28 dB gain, low noise figure (about...
As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the polysilicon electrodes. For the first time, based on least-squares curve fit, we quantitatively explore the impact of quantum mechanics effects in polysilicon gate...
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