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The solder joints model structure of SMT has been established. The general rules of three different positions(the shallow surface, the internal and the interface of solder and pad)were discussed. Then, the finite model has been checked by the combination of experiment and simulation. Finally, through the multi points scanning method, the heat source was applied to heat the solder joints, the temperature...
Through Silicon Interposer (TSI) needs to fulfill multi-die stacking in one packaging which can bring high integration density, short interconnection length and small size for next generation devices. Die stacking is a key process in the TSI manufacturing flow, and within that process, die warpage is of central concern. This is because the large warpage of the Si-mterposer induces poor joining of...
The paper presents the result of studies and investigations related to planar thermoelectric generators, intended to be realized through printing technologies. The recent development in printing technologies and materials makes possible the realization of thermoelectric pairs in planar configuration as an alternative to the already used devices. The use of printing technologies permits the realization...
This paper presents a simulation method for the warpage that take places after the patterning process of printed circuit boards. To conduct an efficient as well as realistic simulation, a nonlinear thermo-elasticity problem with cure kinetics is approximated to a linear one by adjusting the thermal loading condition, which is the processing temperature where the stress-free state is assumed. This...
In recent years, electronic product have been demanded more functionalities, miniaturization, higher performance, reliability and low cost. Therefore, IC chip is required to deliver more signal I/O and better electrical characteristics under the same package footprint. None-Lead Bump Array (NBA) Chip Scale Structure is then developed to meet those requirements offering better electrical performance,...
Microelectronic packages can be considered as composite structures fabricated from highly dissimilar materials. Interface delamination related failure often occurs when the packaged devices are subjected to thermo-mechanical loading. The analysis of delamination of a laminate structure with a crack along the interface is central to the characterization of interfacial toughness. Due to the mismatch...
Interfacial delamination has become one of the key reliability issues in the microelectronics of portable devices and therefore is getting more and more attention. The analysis of delamination of a laminate structure with a crack along the interface is central to the characterization of interfacial toughness. Due to the mismatch in mechanical properties of the materials adjacent to the interface and...
Interfacial delamination is known as one of the root causes of failure in microelectronic industry. In order to explore the risk of interface damage, FE simulations for the fabrication steps as well as for the testing conditions are generally made in the design stage. In order to be able to judge the risk for interface fracture, the critical fracture properties of the interfaces being applied should...
The present stage of development of electronics technology there is an increased interest in the study of new materials used as solder that replaces the already banned tin-lead alloy. Many investigations were done in direction of metallurgic compatibility between the printed circuit board finishing, component terminal finishing and solder itself. Other studies are taken in direction of mechanical...
The study aims at developing a next-generation flip chip (FC) packaging technology that employs a novel anisotropic conductive adhesive (ACF) made of unidirectional Co-nanowire-reinforced polymer nanocomposite, and moreover, exploring the associated process-induced, thermal-mechanical behaviors during bonding process. For carrying out the process simulation, a process-dependent finite element modeling...
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