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Interconnect process features are described for a 32 nm high performance logic technology. Lower-k, yet highly manufacturable, carbon-doped oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever lower metal line capacitance. The pitches have been aggressively scaled to meet the expectation for density, and the metal resistance and electromigration...
65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch...
In this paper a test structure is described which facilitates the evaluation of interconnection schemes for chip on wafer attachment and interconnection. Microinsert technology is described and some of the characterization that the test structure permits is discussed. Thermal cycling experiments were performed on this test structure and although the resistance of the contact chain seemed not to change...
Increased packing density and reduced device size leads to increase in the back-end related delays. This happens as a result of increase in the metal resistance due to decreased line-width and increased capacitance due to a higher density of the interconnects. To minimize the impact of interconnect related delays (RC delay) the semiconductor industry had to, as a first order change, look for metal...
Via and metal resistance, capacitance, stress migration lifetime, and high voltage leakage are characterized for Cu interconnects capped with either CoWP or CoWP + SiN. The CoWP is formed by a self-activated process using DMAB as a reducing agent, providing a very uniform CoWP film. Low via resistance and high stress migration lifetime are observed, even for relatively thin CoWP films without an SiN...
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