The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Characterization of interposer in a 2.5-D stacked IC is essential for yield learning and design optimization. To examine the effect of design parameters of the interposer structure on different substrate materials, the S11 and S21 curves for various substrate materials are obtained from the full-wave simulation. With the simulation results, it is observed that polyimide and glass interposer shows...
Differential through silicon vias (TSVs) are commonly used for the differential signaling in three-dimensional (3-D) integration, which may be disturbed by the electromagnetic field of the neighboring signal/ground paths. In this paper, the equivalent circuit model of the differential TSVs is established. Then the induced noise on the differential TSVs from the neighboring single-ended and differential...
In this paper, we describe the importance of carefully selecting the wafer backside processes in 3D stacked IC process flows. In particular, we report on the impact of TSV Via-middle reveal and backside passivation processes on the C-V characteristic of the TSV. The cause of anomalous C-V inversion of the TSV capacitor is explained and a solution is given to avoid this effect.
Chemical Mechanical Polishing (CMP) on thinned bonded wafer is one of the key challenges in the entire via-last TSV process flow. This paper addresses the issue of oxide loss and barrier metal residue during CMP process. The impact of pre-CMP thermal budget on (i) CMP polishing rate, (ii) uniformity and (iii) selectivity to the underlying dielectric on bonded wafers is investigated. We further looked...
This paper presents a methodology to characterize the electrical behaviors of mixed conventional and coaxial through silicon vias (TSVs) network in three-dimensional (3-D) integrated circuits. An equivalent circuit model is established to predict the insertion loss and crosstalk level of the mixed TSV network. By the proposed model, the shielding effectiveness of the outer conductor in coaxial TSV...
Two vertical transitions with through silicon vias (TSVs) in 3D die stack are designed and their high frequency electrical characteristics are presented in this paper. The two vertical transitions consist of TSVs for obtaining electrical connection between the die front side and back side. Back side redistribution layer is eliminated in the designs to simplify the fabrication process without sacrificing...
To overcome the severe challenges of achieving an extra-thin thickness down to 10 μm for chip stacking of 3D-IC module such as the mechanical damages appear at chip grinding, subsequent steps of wafer handling, and robust assembly, a novel pre-molding technology applied to assembled stacked module prior to chip thinning procedure is presented in this study. Packaging vehicle is fabricated to demonstrate...
TSV-induced stress is extensively studied in silicon interposer by using two different submicron resolution x-ray diffraction techniques. Simulations are performed to interpret the experimental strain results. Stress and strain in silicon are found to be small at room temperature, while measurements and simulations at annealing temperature (400 °C) support a plastic behavior of copper in some regions...
This study presents a new test method for Through Silicon Via (TSV) in 3D stacked ICs, in which a Delay-Locked Loop (DLL) is utilized to detect TSV defects. As compared to TSV test methods using free running ring oscillators, the proposed method presents a much better performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLL systems. In the proposed...
Through-silicon via (TSV) based 3-D ICs provide a promising solution for miniaturizing chips. However, thermal issue in 3-D ICs cannot be ignored. In this paper, we proposed a method based on 3-D transmission line matrix (3-D TLM) method to calculate heat generation in the lossy silicon substrate caused by TSV induced electrical field. Pseudo random bit sequences (PRBS) at different bit rates are...
2.5D and 3D packaging continues to be a popular topic within the semiconductor industry. Several announcements have shown signs of adoption for the new packaging technology, especially for stacked DRAMi. The reveal of the Through Silicon Via (TSV) is a critical step within this packaging integration sequence. However, the biggest challenge delaying high-volume manufacturing is the cost. This article...
Since more chips are fabricated within 3D-IC, the single layer TSV cannot satisfy the requirement. Hence, the multilayer TSV structure was proposed, and the influence of different bump radius, bump height, underfill material in the intermetallic layer on the TSV performance was studied. In reality, multilayer TSV array is applied in the product. Therefore two multilayer 4 × 4 TSV arrays have been...
We have analyzed how the mechanical and geometrical parameters of the Open Through Silicon Vias influence failures induced by delamination of the interfaces. Through Silicon Vias are the units of the interconnection structure that establish the connection through the silicon die. We show that there are different factors that influence the failure of the device by analyzing the effect of external forces...
This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Overview of AMD Radeon R9 Fury; Why HBM and Die Stacking; The Journey to Fury; Performance; Form Factor Innovation.
Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through silicon vias (TSVs) are proposed. The expressions are functions of the geometric and material parameters of TSVs. They also can be applied to the cylindrical TSVs when the slope angle is zero. The two parasitic capacitances increase as the slope angle increases, which implies that the tapered...
In this paper, the CNT TSVs, as well as Cu/CNT composite TSVs, are investigated based on the equivalent circuit model. The effective complex conductivity, which incorporates the kinetic inductive effect of CNTs, has been employed for high-frequency characterization. The performance comparison between Cu, CNT, and Cu/CNT composite TSVs are carried out. It is found that Cu/CNT composite TSVs can be...
In this paper, a systematic test approach is presented for rapid detection of the defects in pre- and post-bond through-silicon vias (TSV). The cylindrical, annular, and coaxial TSVs are studied using the full-wave electromagnetic simulation. The impacts of open and pinhole defects in the pre-bond TSVs can be effectively observed in the Z-parameter variation. Then, a defect detection scheme is developed...
Cu pumping is a potential reliability issue for through silicon via (TSV) based 2.5D and 3D integration, due to the CTE mismatch between silicon and copper. In this paper, we report the reliability assessment of Cu pumping treated at different annealing conditions. Cu pumping is simulated by finite element method to compare the effect of the overburden layer. The pumping of TSVs having a diameter...
This paper presents new TSV-Based applications such as resonant inductive coupling, variable Inductor, power amplifier, bandpass filter, and antenna. These proposed systems use a spiral inductor built using TSV technology. The Resonant Inductive Coupling system increases the amount of magnetic flux linked between coils and improves the power transmission significantly. A proposed architecture based...
In this work we have studied delamination in Open Through Silicon Vias structures under different initial stress loads. The study has been carried out by means of simulation which is based on the evaluation of the J integral for different interfaces. Our simulations enabled us to determine the structures with the lowest failure probability.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.