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The interconnect is the Achilles heel of FPGAs. It currently dominates the delay and leads to high power consumption. It is thus, imperative to take it into account when designing complex FPGA systems. In this work, we propose a learning-based method for data-flow systems build out of multiple individual components directly connected and find a set of optimal configurations with unique area vs. throughput...
Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the...
Physical Unclonable Functions (PUFs) have gained a lot of research attention in recent years resulting in many different PUF proposals. Several of these proposals were aimed specifically at FPGA implementations. However, often these PUFs are evaluated and implemented for different (and often old) FPGA families with different metrics. Missing implementation details in many papers further hamper a fair...
A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an Field...
Due to the widespread use of FPGAs in many critical application domains, their security is of high concern. In recent systems, such as FPGAs in the Cloud or in Systems-on-Chip (SoCs), users can gain access, even remotely, to the reconfigurable fabric to implement custom accelerators. This access can expose new security vulnerabilities in the entire system through malicious use of the FPGA fabric....
ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases...
This paper presents a time-delay system which originally has chaotic behavior, yet lost that dynamic due to finite quantization levels of state variable representation. One method to overcome this destructive effect of digitalization is engaging a time-varying delay amount which is studied in this paper. Based on this system, random number generator (RNG) topologies are demonstrated with better throughput...
Dynamic receive beamforming (DRBF) is challenging for FPGA-based ultrasound (US) imaging because it is computationally intense. Work has been done to either simplify the delay calculation or precalculate the delays and store them on the FPGA. The former sacrifices image quality and the latter is challenged by limited memory resource. In this work, we report on the design of an US imaging system for...
Cellular Automata with Random Memory (CARM), which has been recently introduced, is a time-delay discrete time system such that delay is a random variable. Delay in discrete time systems can be easily generated from a random delay characteristics of wires and transistors in programmable logic devices. Therefore implementation of CARM model is not required any special hardware. In this paper, a new...
The high level of realism of spiking neuron networks and their complexity require a substantial computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically-accurate spiking neuron network is largely set by the high computational and data transfer demands. In this paper, we implement several efficient models of the spiking...
The vision of a software defined radio (SDR) is to implement in different software systems of communications using the same hardware platform. An advanced SDR system consists of two fundamental components: a programmable RF component and another reconfigurable FPGA-based component in charge of performing high-speed signal processing. Since the sampling rate of the ADC and DAC converters is generally...
For time-of-flight positron emission tomography detectors, time-to-digital converters (TDCs) are essential to resolve the coincidence time of the photon pairs. Recently, an efficient TDC structure called ring-oscillator-based (RO-based) Vernier TDC using carry chains was reported by our team. The method is very promising due to its low linearity error and low resource cost. However, the implementation...
Hierarchical routing resources play vital role in FPGA routing. Better routability options can be obtained using segmented approach of wires thus enabling routing optimization. Source and sink logic blocks can be connected via wire segments such that the overall wire length and switching transistors inside the switch box can be saved over an extent. This paper presents an experimental approach of...
Silicon based Physical Unclonable Function (SPUF), a chip level identifier that utilizes the inherent irregular manufacturing process variations, can be extended to Ring Oscillator PUFs (ROPUFs). The ROPUF structure, although promising for FPGA based platforms, is not area efficient in terms of response bit per RO circuit implementation. This paper introduces an area efficient Stage Configurable ROPUF...
Random sub-sampling imaging methods in Atomic Force Microscopy require the piezo X-Y stage to track a sequence of step inputs. Control slew-rate limits combined with linear feedback methods have been shown to limit achievable performance in this scenario. Due to its natural ability to account for actuation constraints, we consider the application of Model Predictive Control. By recasting the problem...
Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
Library based design and IP reuse have been previously proposed to speed up the synthesis for large-scale FPGA designs. However, previous library based design flow faces several unresolved challenges. Firstly, they may result in large waste area between the modules due to the difference in module sizes. While utilizing multiple ratio modules can help to reduce the waste area, pre-synthesis each module...
In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas,...
In this paper, we aim at increasing the strength of weak arbiter physical unclonable function (APUF) which are vulnerable to modeling attacks because of low uniqueness and randomness. We propose a unique technique which takes n × 1 challenge-response pairs (CRPs) from APUF and combines them with ring oscillators (ROs) implemented on the same FPGA to get n × n CRPs. We claim the proposed technique...
This paper presents a design of an on-chip single event transient (SET) pulse width measurement system. The proposed system has been designed and implemented in IHP's 250 nm bulk CMOS technology and is intended for evaluation of SET effects in standard digital library cells. It is composed of an inverter-based target circuit, a pulse stretcher and a processing unit for counting the SET pulses and...
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