The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.
This paper describes the systematic design of a high speed and high resolution CMOS Flash Analog-To-Digital Converter. A 7-bit flash ADC is implemented in cadence environment using gpdk90-nm CMOS technology with a 1.2-V analog supply voltage. The converter achieves a signal-to-(noise + distortion) ratio of 39.3574dB and signal-to-spurious-free-dynamic-range of 40.7547dB with a sampling rate of 500MHz.
This paper presents a high-voltage output stage producing signals well beyond the voltage ratings of standard devices in a nanometer-scale CMOS technology. The driver is a two-level, switched capacitor output stage that combines both voltage conversion and pulse drive. The design is highly modular and enables extended device-stacking seamlessly and with little overhead. The driver achieves a peak...
The method of increasing (by 5÷10 times) of the voltage transfer ratio (Gain) of the broadband cascode amplifiers (BCA) with the passive load in the form of the relatively low-ohmic resistor (R1=0.5÷1 kOhm) is considered. The effect of the increase of the gain of BCA is provided due to the introduction of a special circuit of the inherent compensation R1. The architectures of BCA on the bipolar and...
This paper shows a methodology to reduce electromagnetic radiation in typical CMOS digital systems from chip PDN design point of view. Total PDN property with anti-resonance peak can be strongly affected by on-die PDN property. Then, in order to suppress anti-resonance peak in total system PDN, design of chip PDN is more effective than off-chip damping method. Then, two similar test chips were designed...
In this paper, an ultra low power CMOS-only voltage reference is presented. The reference exploits the work function difference between anti-doped (flipped-gate) and standard-doped nMOS devices. These devices require no additional processing and are realizable from the basic N+ and P+ implants used to implement the standard enhancement mode MOS devices on the process. The reference is implemented...
This paper proposes a pulse-controlled common-mode feedback circuit for a supply-scalable fully-differential amplifier. The pulse-controlled common-mode feedback circuit overcomes the large area cost associated with a conventional R-C common-mode feedback circuit while maintaining high gain and large output signal range of the amplifier. The amplifier is implemented in low power/leakage 65nm CMOS...
The most difficult fault category in electronic systems is the “No Fault Found” (NFF). It is considered to be the most costly fault category in, for instance, avionics. The relatively few papers in this area rarely deal with analogue integrated systems. In this paper a simple simulation model has been developed for a particular type of NFF, the intermittent resistive fault resulting from bad interconnections...
Low-resistance lateral pin junctions for LDs on III-V CMOS photonics platform are obtained using Si implantation and Zn diffusion owing to high thermal tolerance of III-V-OI wafer, resulting in observing electro-luminescence from Inga Asp photonic-wire waveguides.
Users of test equipment such as oscilloscopes expect performance and accuracy beyond the level of their device under test in order to insure measurement results correspond to the DUT, not to limitations of the test equipment. This drives the use of bipolar circuitry at the front-end of high-bandwidth oscilloscopes, even if targeted at testing devices in a marketplace dominated by CMOS. Several circuit...
The main goal of this paper is investigation of the fault coverage dependence on the value of the oscillation frequency in oscillation-based tests of analog circuits. For this purpose, an operational amplifier designed in 90 nm CMOS technology was used as a Circuit Under Test (CUT) in our experiment. Then, the CUT was transformed into an oscillator and different catastrophic faults were considered...
Second and fourth order reconfigurable filter structure implemented with second generation current controlled current conveyor is presented in this paper. Reconfigurable filter structure is widely used on the basis of the encrypted communication, cognitive radio and software defined radio systems. The designed filter is applied to the global positioning systems (GPS, GLONASS, Beidou, GNSS and Galileo)...
An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2...
This paper discusses and shows the use of Nauta operational transconductance amplifiers as integrator elements in a second-order continuous-time delta-sigma ADC. The structure is studied in order to take advantage of its potentially high bandwidth operation and simple inverter-based structure for wide output voltage range in current and future CMOS process. The second-order continuous-time delta sigma...
In this paper, a new realization of a first-order voltage-mode (VM) All-Pass Filter (APF) using a grounded capacitor, three resistors, and a single Current Follower (CF) with non-unity gain is presented. The number of external resistors in the proposed VM APF can be reduced to two by considering the input intrinsic resistance of the CF as a useful active parameter. In comparison to the second-generation...
In this work a comprehensive SPICE model is demonstrated for perimeter-gated single photon avalanche diodes (PGSPAD) fabricated in commercial 0.5 µm CMOS process. This model simulates the trigger of an avalanche event of PGSPAD due to photon absorption, along with the quenching behavior. It also simulates the I–V characteristic, where the breakdown voltage can be modulated with applied gate voltage...
This work proposes the use of non-recursive factored forms in material implication logic as a way to increase performance with a small additional cost in the number of required devices. Previous works addressing memristor based implication logic focus only on recursive forms. The utilization of factored forms can reduce the number of operations. Since this kind of logic is naturally sequential, the...
This paper presents an alternative linear topology for conditioning resistive sensors. This topology allows us to obtain an inherently linear relationship between the variable measured by the sensor and its corresponding output, which is not always valid for the topologies most commonly employed in industrial applications, such as the Wheatstone bridge. SPICE simulations of this alternative topology...
The co fabrication of S ET & CMOS technology has already proved its ability to bring a drastic change in the era of nanodimensional devices. In our present work a well known combinational circuit, octal to binary encoder is demonstrated using hybrid SET-CMOS technology in 22 nanometer node. We have presented power analysis for the circuit here. Power delay product for the circuit has also been...
Copper metal gate has been introduced in logic CMOS processes starting from the 45-nm technology node. With the skin depth of about 270 nm at 60 GHz for copper, the DC end-to-end resistance of the copper gate electrode is found to be Rdc ≈ 9 Ω for a 45-nm MOSFET with W/L = 30 and it is a good estimation of the actual effective resistance Rac with less than 1% error. Rac of copper-gate electrode with...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.