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We show, for the first time, a reversal in net interface dipole polarity (initially n-type) for a metal gate stack by forming p-type interface dipoles after a 950degC anneal. This was achieved in both TaN/SiO2 and TaN/high-k gate stacks whereby terbium (Tb) and aluminum (Al)-based interlayers were used to form n-type and p-type dipoles, respectively. We also demonstrate the continuous tunability of...
This study, the performance of the (In0.1Ga0.9N/SiC/Si) solar cell was theoretically designed and investigated. The design and performance evaluated by developing simulation models that are included in our simulator (ISE TCD). The limitation of the current versus voltage and efficiency values will be discuss and analyze. The calculation of current and voltage has been done under AM 1.5 with doping...
Effect of the flat band voltage reduction (roll-off) in highly scaled high-k/metal gate stacks is discussed. The proposed mechanism explains the roll-off phenomenon as caused by the metal electrode/high-k dielectric-induced generation of positively charged oxygen vacancies in the interfacial SiO2 layer in the high-k dielectric stack. The model is consistent with the observed roll-off dependency on...
Silicon nanowire based discrete trapped charge-storage nonvolatile memory cell employing high-kappa dielectrics with metal gate is presented for the first time. The nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si) memory fabricated using top-down method in nearly gate-all-around (GAA) architecture showed higher P/E speed than SONOS. In TAHOS, the erase speed is found almost equal to the program speed. The...
The photoluminescence of silicon-rich silicon nitride (SRSN) film was enhanced by coupling with the localized surface plasmon of Ag island film. It is found that the deposited Ag film induces an enhancement of excitation of SRSN film through increasing the absorption of SRSN film. Furthermore, it is demonstrated that the emission enhancement is much more decided by the excitation wavelength than by...
Silicon carbide has long been hailed as the successor to silicon in many power electronics applications. Its superior electrical and thermal properties have delivered devices that operate at higher voltages, higher temperatures and with lower on-resistances than silicon devices. However, SiC Schottky diodes are still the only devices commercially available today. Though SiC Schottkys are now being...
A method of directly patterning silicon dioxide layers without the use of a mask is described. The method uses an inkjet device for the patterned deposition of a solution containing fluoride ions onto an acidic water-soluble polymer layer formed over the silicon dioxide. The deposited solution reacts with the polymer layer, at the locations where it is deposited, to form an active etchant that etches...
In summary, we successfully demonstrate the unpinning of the Fermi level in n-GaAs through the insertion of an ultrathin insulator to reduce the penetration of MIGS from the metal into the semiconductor. We are able to transform the current from rectifying Schottky behavior, to increased conduction, to tunneling limited, simply by increasing the SiN thickness, verifying the ability for SiN to modulate...
We demonstrate a self-aligned process for forming fully- depleted SOI MOSFETs with deposited metal-silicon S/D junctions and gate lengths as short as 75 nm. For the devices presented here, the metal S/D regions were formed of deposited Al which is self-aligned to the gate and STI edges, with Si3N4 junction passivation to suppress Fermi-level pinning. Inverse modeling of the electrical data indicates...
The large negative Vfb shift by capping a thin layer of Me2O3 (Me= Gd, Y or Dy) on SiO2 and HfO2 with TaN metal gate was investigated. It was found that the negative Vfb shift is due to the dipole formation at MeSiO-SiO2 interface. The local bonding asymmetry is proposed to be the underlying reason for the dipole formation.
Reliabilities of high-k stacked gate dielectrics are discussed from the viewpoint of the impact of initial traps in high-k layer. TDDB reliability can be explained by the generated subordinate carrier injection (GSCI) model. While initial traps increase the leakage current, they do not degrade the TDDB reliability. In contrast, the BTI reliability is strongly degraded by initial traps.
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiOx interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With...
A new approach is proposed to predict the silicon content in hot metal with neural network trained by chaos particle swarm optimization. Firstly, an advanced particle swarm optimization algorithm based on chaos search(CPSO) is presented to enhance the local searching ability and improve the convergence speed. Then CPSO is applied to train neural network and a model to predict the silicon content in...
We successfully demonstrated Schottky barrier height modulation in metal/Ge Schottky junction by inserting an ultrathin interfacial SiN layer. The SiN layer suppressed strong Fermi level pinning in metal/Ge junction, which resulted in effective control of the Schottky barrier height. We systematically investigated its physics, for the first time, and almost zero Schottky barrier height was successfully...
This paper discusses a role of the oxygen vacancy in HfO2/ultra-thin (UT) interfacial layer (IL) SiO2 gate stacks, focusing on the VFB roll-off. The metal/top-SiO2/HfO2/UT IL-SiO2/Si gate stacks have been studied. It is found for the first time that the VFB roll-off is eliminated by inserting 1~2 nm top-SiO2 between metal gate and HfO2. This elimination of the VFB roll-off is explained by compensating...
We demonstrate midgap and band-edge effective workfunctions (EWFs) control with simple metal gate process scheme (singlemetalgate/singlegatedielectric), using impurity-segregated NiSi2/SiON structure for embedded memory application. The application of midgap and band-edge EWF enables us to lower power consumption in SRAM and logic devices by 30% and 15% compared to poly-Si devices, respectively,...
In this paper, we present a much simpler implementation of the double tunnel junction by utilizing the monodisperse nature of these nanoscale entities. C60 molecules instead of Si NCs are embedded inside the oxide barrier to overcome the limitation on the NC size control. We will further show improved tR I tPE ratio in a metal NC memory integrated with this barrier.
Active photonic devices like efficient light emitters and high speed modulators using Si and other group IV materials are difficult to realize due to indirect nature of band gap in silicon, germanium and their alloys. At present, efficient light emission has been observed by exploiting stimulated Raman scattering in silicon that needs optical pumping. An alternate route has been found recently that...
SONOS-type NAND flash memory cell with metal-Al2O3-SiN-Si3N4-Si was fabricated and key characteristics were investigated. Low voltage and high-speed programming/erasing characteristics were achieved, due to low barrier height of Si3N4 and high dielectric constant of Al2O3 compared with those of SiO2. It also showed good endurance up to 10 k cycles, and more than 1.5 V memory windows after 10 years.
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