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In this paper, we focus on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional...
Increase in variability in the nanometer era has contributed to pessimistic guardbands for conventional circuit design techniques that optimize at worst-case process corners. Smart deterministic approaches have been proposed that employ statistical timing analysis to reduce pessimism in the guardbands while retaining the deterministic nature of the algorithms. Other statistical optimization techniques...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
Various comparator designs that are suitable for current device technology are shown. The designs are based on LSB-first or MSB-first approaches. Linear operation time designs are derived as the first step. O(log n) operations time with O(n) or O(n log n) hardware cost are attained by parallel implementation of prefix operations and reductions.
Circuit design often runs in parallel with the development of the manufacturing process that will be used to fabricate it. However, as the manufacturing process matures, its models may undergo substantial changes as the design nears production. These changes may cause the design itself to fail its specifications, and in these cases it is necessary to perform an Engineering Change Order (ECO) to correct...
Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtraction operations, they do not consider the low-level implementation issues that directly affect the area, delay, and power dissipation of the MCM design. In this paper, we initially present area efficient addition and subtraction...
In this paper, we introduce a design methodology to implement low-complexity and high-speed digital Finite Impulse Response (FIR) filters. Since FIR filters suffer from a large number of constant multiplications, in the proposed method the constant multiplications are replaced by addition/subtraction and shift operations. Also, based on the design objective, i.e., low-complexity or high-speed, the...
Wireless mesh networks (WMNs) have gained tremendous popularity as a cost effective and reliable solution to last-mile broadband Internet connectivity. However, the network design without global information is a challenging task. We study the optimal network topology design problem in WMNs and propose an ant-based cognitive networking algorithm to search a topology with the minimum cost while guaranteeing...
In a digital circuit system, IR drop effect can be alleviated by reducing the peak current of the system. Clock skew scheduling is a popular technique for peak current reduction. In this paper, we propose two algorithms that apply a Multiple Threshold CMOS (MTCMOS) technique rather than clock skew scheduling to do peak current reduction. MTCMOS techniques are feasible to reduce peak current because...
In this paper, we present an enhanced priority encoder, called full parallel priority encoder (FPPE) that can be used in the comparator circuitry. Because there is no serial NAND-type path, the performance of FPPE is better than that of the conventional priority encoder. The comparator with FPPE is implemented in UMC 90nm CMOS technology. The simulation results show that the proposed design is 40%...
Stored Unibit Transfer (SUT) has been recently proposed as a redundant high-radix encoding for the channels of a Residue Number System (RNS) that can improve the efficiency of conventional redundant RNS. In this paper we propose modulo 2n±1 forward and reverse converters for the SUT-RNS encoding. The proposed converters are based on parallel-prefix binary or modulo adders and are therefore very efficient.
This study investigates the relative performances of Array, Wallace, Dadda and Reduced Area multipliers for several synthesis optimization modes. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 0.35-micron ASIC Design Kit standard cell library. Performance data was extracted after logic synthesis in LeonardoSpectrum for Area, Speed and Auto optimization modes....
In this paper, the new clock distribution design flow and algorithm of clock gate splitting to improve the clock gate's enable signal timing violations had been presented. The clock gate components in a clock tree are exposed to setup timing violations due to the nature that the clock gates skew is normally big as they are located at the beginning of the clock tree. The effective splitting of the...
This paper describes an approach of using a multi-objective fitness function to improve the performance of digital circuits evolved using CGP. Circuits are initially evolved for correct functionality using conventional CGP before the NSGA-II algorithm is used to extract circuits which are more efficient in terms of design complexity and delay. This approach is used to evolve typical digital-system...
In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial...
This paper presents a bit serial realization of the sign-LMS based adaptive filter which enjoys multiplier free weight update loop. To reduce the complexity of the multipliers that arise in the filtering process, the filter weights are represented in the so-called canonic SPT form which guarantees presence of at least one zero between every two non-zero power-of-two terms. As the filter weights are...
Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event...
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasing circuit complexities, including the need to analyze circuits with billions of transistors, across potentially thousands of process corners, with accuracy tolerances down to the picosecond range, sequential execution of...
This paper introduces a novel one-step digital control technique that can dynamically optimize the dead-times for the turn-on and turn-off of the power MOSFETs in DC-DC converters. A NOR gate and a delay-line circuit are used to detect and measure the duration of the unwanted low-side MOSFET body-diode conduction. Based on this measurement, the optimum dead-time is calculated on-the-fly and the DPWM...
Near-Threshold Circuits achieve ultra-low energy operating with significant performance improvement and noise immunity as compared to sub-threshold circuits. However, near-threshold circuit performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance...
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