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A high voltage mixed signal ASIC is described that provides multiple fully programmable clock outputs capable of driving large format CCD capacitive electrodes. The COMET ASIC provides 6 independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that...
A capacitor-less low drop-out (LDO) regulator for SoC applications with buffer based compensation technique is proposed in this paper. The 1.6 V LDO with a power supply of 1.8 V is implemented in GPDK 0.18 μm CMOS technology and it achieves a PSRR of 70 dB up to 1 kHz for load currents up to 10 mA. It makes use of PMOS folded cascode error amplifier to lower the flicker noise. Simulation results verify...
A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0–50 mA with a rise time of 1 µs results in an undershoot in the output voltage...
In this paper, a three-stage Voltage Controlled Ring Oscillator, designed and implemented using IBM 130nm CMOS technology with Cadence Virtuoso tools, is presented. The initial specification for the output frequency is 400MHz–1GHz, but our proposed design could generate the oscillation range from 82.72KHz to 1.49GHz when control voltage is from 0.0V to 1.2V. Furthermore, the power consumption is extremely...
A two-step offset correction technique for high precision comparator design is proposed. The two step coarse-fine calibration (CFC) technique provides precise offset correction much faster than a single step calibration and the circuit implementation is less complicated. The proposed two step calibration technique was employed on a two-stage dynamic latched comparator using 0.35μm CMOS process. The...
As the technology improved to support very large chip sizes, system designers were faced with power consumption problem and leakage current problem. CMOS technology has increased in level of importance to the point where it now clearly holds center stage as the dominant VLSI technology In this research paper shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable...
This article presents a universal amplifier module (UAM), implemented in 180 nm CMOS technology, that can be configured to function as a (i) voltage controlled voltage source (VCVS), (ii) current controlled current source (CCCS), (iii) voltage controlled current source (VCCS), (iv) current controlled voltage source (CCVS), and (v) current conveyor (type II). As a result, the amplifier can be used...
A programmable voltage reference used in an advanced wafer-scale hierarchical voltage regulation circuit is presented. The novel arborescence structure of the voltage regulation system is described and the requirements for the voltage reference derived. The proposed programmable voltage reference is based on beta-multiplier architecture, implemented in 0.18 μm CMOS technology with a very small area...
A fully configurable bias current reference is described. The output of the current reference is a gate voltage which produces a desired current. For each daisy-chained bias, 32 bits of configuration are divided into 22 bits of bias current, 6 bits of active-mirror buffer current, and 4 bits of other configuration. Configuration of each bias allows specifying the type of transistor (nfet or pfet),...
This paper describes an ultra-compact analog lithium-ion (Li-ion) battery charger for wirelessly powered implantable medical devices. The charger presented here takes advantage of the tanh output current profile of an operational transconductance amplifier (OTA) to smoothly transition between constant current (CC) and constant voltage (CV) charging regimes without the need for additional area- and...
In this paper, we present a low dropout voltage regulator (LDO) which can be programmed to generate four output voltages (3.3 V, 2.5 V, 1.8 V, and 0 V) by the external control signals. Between the error amplifier and the power transistor, we place a simple buffer so that the power supply rejection (PSR) of LDO can be improved. The design specification of the maximum load current is 100 mA. The proposed...
In this paper, the development of a low drop-out voltage regulator with multiple enable controls was described. In circuit design, a lateral PNP transistor was used as a regulating transistor, and combined band-gap reference and feedback were adopted. The low drop-out voltage regulator was processed in 0.5 um BCD process technology. It has multiple enable control. The output current was 100 mA, the...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
This paper will present a very compact EEPROM cell for high density applications, featuring split voltage programming. The information is stored in a self-aligned floating-gate transistor with thin (8nm) tunnel oxide. Bit selection is performed by a low-voltage transitor. Long endurance (more than 106 cycles) is achieved and the asymmetric window closing will be explained. The innovative cell concept...
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