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This paper presents a novel CMOS folded cascode operational amplifier that leads to high PSRR and provides gain nearly equal to that of a two stage op-amp. The proposed design is implemented in GPDK 0.18μm CMOS technology. This op-amp uses a folded cascode structure in the output stage combined with the differential amplifier having PMOS input transistors to achieve good input common mode range and...
A capacitor-less low drop-out (LDO) regulator for SoC applications with buffer based compensation technique is proposed in this paper. The 1.6 V LDO with a power supply of 1.8 V is implemented in GPDK 0.18 μm CMOS technology and it achieves a PSRR of 70 dB up to 1 kHz for load currents up to 10 mA. It makes use of PMOS folded cascode error amplifier to lower the flicker noise. Simulation results verify...
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