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Based on a variety of long-term network traffic data from different geographies and applications, in addition to long-term scaling trends of key information and communication technologies, we identify fundamental scaling disparities between the technologies used to generate and process data and those used to transport data. These disparities could lead to the data transport network falling behind...
Small ARM Cortex-M0 PC boards MARY linkable to form an array network for parallel processing were applied to realtime multi-tasking DSP. Multiple MARY boards coordinate the multi-tasking DSP process via four directional communication ports of (N, S, W, E) without using the shared memory like the Transputer (developed in 1980's) works. The validity of the Transputer concept applied to a low-end embedded...
Low power multipliers with high clock frequencies play an important role in today's digital signal processing. In this work, the performance analysis of Wallace-tree, Array and Baugh-Wooley multiplier architectures is carried out. Physical verification of all the sub-blocks is performed using HSpice to check their functionality and to optimize for low power by using transistor sizing. The layouts...
In this paper a coarse-grain dynamically reconfigurable coprocessor for image processing is presented. This coprocessor is the main component of a System on a Programmable Chip (SoPC). The coprocessor can accelerate a wide range of image processing tasks and can be configured in a few clock cycles. The coprocessor performance and reconfiguration functionality has been tested with algorithms that involve...
Microprocessor and DSP are optimized to perform operations on data having the same size of native wordlength. Their performances decrease when shorter data must be processed. In fact, operations on a short data have the same complexity native wordlength data and data resources are not fully exploited. Recently different solutions have been proposed to overcome this problem. Great attention has been...
This paper presents a reconfigurable systolic array design suitable for multi-carrier wireless applications. The systolic array architecture includes coarse grained processing elements and interconnection switches. The systolic array can be configured as a Polyphase-FIR filter, DFT, Polyphase-DFT and IDFT-Polyphase function. A representative reconfigurable circuit has been designed and implemented...
2D operators were categorized based on their implementation methods on different low-power topographic and non-topographic single-chip processor architectures. The implementation methods of the 2D operators in the individual categories are shown, and their processor utilization efficiency is analyzed. The execution times of the basic operators on the different architectures are calculated, the power...
This paper presents a parameterization concept for the automatic layout generation of multipliers in digital signal processing. Based on a hierarchical cell design methodology the layout of parameterized two's complement bit-parallel multipliers can automatically be generated according to any desired wordwidth of multiplicand and multiplier. Additionally the product can be rounded or truncated to...
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