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In this paper a coarse-grain dynamically reconfigurable coprocessor for image processing is presented. This coprocessor is the main component of a System on a Programmable Chip (SoPC). The coprocessor can accelerate a wide range of image processing tasks and can be configured in a few clock cycles. The coprocessor performance and reconfiguration functionality has been tested with algorithms that involve...
This paper presents a reconfigurable systolic array design suitable for multi-carrier wireless applications. The systolic array architecture includes coarse grained processing elements and interconnection switches. The systolic array can be configured as a Polyphase-FIR filter, DFT, Polyphase-DFT and IDFT-Polyphase function. A representative reconfigurable circuit has been designed and implemented...
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