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Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing...
To handle the expected increase in data rate of the LHCb experiment after the upgrade, a new FPGA based DAQ system has been proposed. As a part of this new DAQ system a Dynamically Adaptive Header Generator has been designed and implemented to packetize the streaming data coming, from the Front-end electronics of the detectors, for easy access and processing by the Servers. This module also dynamically...
Simulation of digital communication systems for the evaluation of bit error rate (BER) and other performance characteristics can be accelerated if the processing is implemented in programmable gate array (PGA) hardware. These simulations often require one or more Gaussian distributed pseudorandom number sources. Although uniformly distributed pseudorandom number sources can be readily implemented,...
This paper presents a method for generating chaotic pseudo random (PR) sequence, which uses a novel three-dimensional (3-D) chaotic system and can generate both digital chaotic PN sequences and continuous time chaotic noise signals. This technique is derived from the idea of combining DSP builder tool with Matlab/Simulink and Quartus II software and is based on the direct discreteness and quantization...
Dynamic and partial reconfiguration allows to place on line the various tasks that describe an application, in available regions of an FPGA. This new feature leads notably to communication problems since tasks are not present in the matrix during all computation time. In this article, we compare popular interconnection architectures. From this study, the DRAFT network is designed to support the communication...
Decimal floating point (DFP) operations are very important for applications, that cannot tolerate errors from conversions between binary and decimal formats, for instance scientific, commercial, financial and internet-based applications. In this paper we present a parallel decimal fixed-point multiplier, designed to exploit the features of FPGAs. Our multiplier is based on BCD recoding schemes, fast...
We envision that future field-programmable gate arrays (FPGAs) will use a hardwired network on chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a 3-tier reconfiguration model that uses the HWNoC as the underlying platform to realize dynamic loading, starting, and stopping of applications...
This article mainly describes a way of designing an efficient pseudo-random number generator. Combining that the cellular automaton has many characteristics, such as simple rules of the component units, the local connectivity of units, the high degree of parallelism in information processing, and the complicated global characteristics, we use the rule 30 of one-dimensional cellular automaton to drive...
In order to solve the question for the 32-bit multiplier to do a variety of bit-length multiplication fast in the form of reusing resource on the FPGA, radix-4 booth modified algorithm is studied, and a bit-length controller is designed to control some bits, partial product generator and fast adder's structure are improved, so as to reuse most of the hardware resource in 8-bit or 16-bit multiplication...
A neural network controller is designed for DC-DC buck converter, and hardware implementation problem of the controller is discussed based on FPGA.The reconfigurable features of neural network controller is analyzed in the article, the controller is built to achieve the model based on SG/Simulink and three basic reconfigurable units was given. The simulation results show that the FPGA-based reconfigurable...
In this paper, we propose a new parallel-pipeline approach to design small-area low complexity convolutional encoders, suitable for high data throughput communication applications. This approach can apply both to the OTM (one to many) and the MTO (many to one) encoder schemes. Here, we will discuss the problem of designing a low cost parallel-pipeline encoder for the MTO case. The new architecture...
Synthetic Floating-Point (SFP), a synthetic benchmark generator program for floating-point circuits is presented. SFP consists of two independent modules for characterisation and generation. The characterisation module extracts key dataflow statistics of an arbitrary software program. Generation involves producing randomised circuits with desired statistics which are either the output of the characterisation...
This paper presents a compact implementation of the S-Box of Pomaranch stream cipher using composite field arithmetic in GF((23)3). It describes a systematic exploration of different choices for the irreducible polynomials that generate the extension fields. It also examines all possible transformation matrices that map one field representation to another. We evaluated the optimal candidates using...
This paper presents a new method for creating TRNGs in Xilinx FPGAs. Due to its simplicity and ease of implementation, the design constitutes a valuable alternative to existing methods for creating single-chip TRNGs. Its main advantages are the high throughput, the portability and the low amount of resources it occupies inside the chip. Therefore, it could further extend the use of FPGA chips in cryptography...
In this paper many spread-spectrum schemes, several of which are new, have been designed and implemented for conducted-noise reduction in DC-DC converters. A field-programmable gate array (FPGA) has made substantial improvements in price and performance throughout the past few years. The implementation of the schemes has been accomplished by using FPGA-based controller. A breadboard circuit has been...
A novel technique for conducted-noise reduction has been proposed in this paper. The proposed technique uses three randomized parameters for generating the switching signals. These parameters are carrier frequency, duty-ratio, and the pulse position. This triple-hybrid spread-spectrum technique has been designed and implemented using field-programmable gate array (FPGA) technology. Moreover, the effect...
Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses...
Software defined radio (SDR) is gaining much attention in many application fields, e.g. satellite communication (SATCOM). In this paper, the requirements of SDR architecture for SATCOM application are discussed and a novel network on chip (NoC) architecture proposal are presented in order to achieve these requirements. Compared with several common NoC architectures, the proposed NoC can reduce the...
To unveil the potential of reconfigurable systems, strong tool support is required. In particular the modeling and implementation of designs to be executed using the partially reconfigurable capability of modern FPGAs is challenging and hardly supported by current design tools. A key problem thereby is the generation of partial bitstreams. The presented design tool Part-E tackles these challenges...
We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit generator...
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