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Video coding has become widespread through mobile devices. At the same time, the adopted resolutions have been enlarged, demanding more coding efficiency and motivating the development of the new state-of-the-art standard, High Efficiency Video Coding (HEVC). However, to achieve the required efficiency the new standard greatly increased the computational intensity. That, allied to real-time constraints...
The increasing resolutions combined with storage and processing limitations of mobile devices point to the need for new compression techniques for video coding. Meanwhile, to achieve higher compression rates without compromising quality, the coding process becomes more and more complex. In reference software of HEVC the most time consuming step is the execution of Motion Estimation (ME), which is...
Many software mechanisms for geophysics exploration in Oil & Gas industries are based on wave propagation simulation. To perform such simulations, state-of-art HPC architectures are employed, generating results faster and with more accuracy at each generation. The software must evolve to support the new features of each design to keep performance scaling. Furthermore, it is important to understand...
The currently used hardware validation architectures for Application Specific Integrated Circuits intended for automotive Engine Control Unit development are reviewed and a new architecture is proposed. An alternative to hardware validation by different simulation architectures is proposed and analyzed.
Scalar addition and multiplication generally obey commutative and distributive laws. However, in their hardware implementation, error propagation and accumulation do not necessarily follow the same rules. In this paper we present a statistical analysis of the accuracy in complex multiplication approaches for IEEE 754 single precision operands. Several approaches were evaluated using a dual approach...
Sparse Code Multiple Access (SCMA) is a promising multiple access technology candidate for 5G wireless communication systems. The high detection complexity is its bottleneck. Stochastic computation is an ultra-low complexity digital signal processing technique in which probabilities are represented and processed with streams of random bits. In this paper, we propose a novel low complexity stochastic...
Hardware realization of fast Fourier transform (FFT) function consists of multiple complex arithmetic operations. Floating point implementation of FFT provides wider dynamic range than their fixed point counterparts and fusing the floating point arithmetic operations inside the Butterfly unit of FFT improves the speed of operation. This paper presents an FFT implementation using a fused four term...
Model predictive control (MPC) is a popular advanced model-based control algorithm for controlling systems that must respect a set of system constraints (e.g. actuator force limitations). However, the computing requirements of MPC limits the suitability of deploying its software implementation into embedded controllers requiring high update rates. This paper presents a scalable embedded MPC controller...
High level hardware simulation and modeling techniques matured significantly over the last years and have become more and more important in practice, e.g., in the industrial hardware development and automotive domain. Yet, there are many other challenging application areas such as numerical solvers for environmental or disaster prediction problems, e.g., tsunami and storm surge simulations, that could...
Emerging neural hardware substrates, such as IBM's “TrueNorth” neurosynaptic system, can provide an appealing platform for deploying numerical algorithms. For example, a recurrent Hopfield neural network can be used to solve for the Moore-Penrose matrix inverse, which enables a broad class of linear optimizations to be solved efficiently, with very low energy cost. However, deploying numerical algorithms...
Live Virtual Machine (VM) migration offers a couple of benefits to cloud providers and users, but it is limited within a data center. With the development of cloud computing and the cooperation between data centers, live VM migration is also desired across data centers. Based on a detailed analysis of VM deployment models and the nature of VM image data, we design and implement a new migration framework...
In this digital information explosion era, more and more products are proposed to enhance the quality and convenience of our life. However, vision-based hand gesture recognition is still a challenging problem to overcome. In this paper, an architecture system was proposed with dual-camera to construct the depth map and recognize dynamic hand gesture. It contains one static and two dynamic hand gestures...
Evaluating cache performance is becoming critically important to predict the overall performance of out-of-order processors. Non-blocking caches, which are very common in out-of-order CPUs, can reduce the average cache miss penalty by overlapping multiple outstanding memory requests and merging different cache misses with the same cacheline address into one memory request. Normally, memory-level-parallelism...
Division is a fundamental operation used in the architectures for digital signal processing algorithms. In this paper, we propose a fixed-point divider based on an ensemble of moving average (EnMA) curves. The EnMA algorithm generates piecewise polynomial explicit functions, which are first-order continuously differentiable. Thus, applying the EnMA algorithm for generating the curve y = 1/x, we directly...
In this paper, a new boost-flyback converter topology for a Differential Power Processing(DPP) System in feed-forward type is proposed. Output of photovoltaic(PV) panels are connected in series, each of them is attached to DPP converter and then the output of the DPP converters are coupled in series. These outputs of the DPP converters need to balance the voltage each other to ensure the proper working...
In this paper, we present a novel hardware implementation of a watermarking system applied on the digital image. The proposed hardware system is based on the DWT (Haar discrete wavelet transform) on the first level of the decomposition. The watermark is hidden in the LH0 (mean frequency sub-band) in goal to get a maximum of the compromise between the visibility and the robustness factors against several...
Understanding and modeling the brain is one of the key scientific challenges in the twenty-first century, and a grown effort is rising on a global scale. Due to its high parallelism, the hardware implementation of large-scale spiking neural networks (SNNs) promises superior execution speed compared to sequential software approaches. Such systems can significantly benefit from the use of networks-on-chip(NoC),...
An improved DNA sequence alignment scheme using a matrix named neighbouring matrix is presented in this paper. This paper also presents a simple design of the hardware implementation of the proposed global sequence alignment approach to meet the requirement of high speed processing. Additionally, this architecture efficiently uses SRAM to boost DNA sequence alignment in real time by employing a few...
The recursive filter (IIR) parallel programming on SIMD is more difficult than that of nonrecursive algorithms due to data dependency. Several transformation methods for parallel coding of IIR filter on SIMD have already been proposed to deal with data dependency. However, the inherent prologue and epilogue in these methods obviously increase the complexity of control structures and induce extra hardware...
Physically Unclonable Function (PUF) is cost effective and reliable security primitives widely used in authentication and in-place secret key generation. With growing research in the area of non-CMOS technologies for memories and circuits, it is important to understand their implications on the design of security primitives. Resistive Random Accessible Memory (RRAM) offers easy integration with CMOS...
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