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In this paper, we propose a new voltage controlled oscillator (VCO) with a high oscillation frequency yet low power consumption. The oscillator which is a single stage circuit has a low phase noise due to reduced noise sources. To evaluate the performance parameters, the oscillator was simulated in a 0.18-μm standard CMOS process. The results show that the oscillation frequency of VCO may vary between...
A 40GHz wide-locking-range frequency divider and a low-phase-noise VCO are implemented in 0.18mum CMOS technology. The frequency divider demonstrates a locking range of 10.6GHz with 0dBm input power while the VCO exhibits a phase noise of -108.65dBc/Hz at 1MHz offset. Each of the 2 circuits consumes 6mW from a 1V supply.
This paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized with pMOS transistor, thus relaxing the sensitivity to substrate-induced noise and flicker noise (1/f) effect. A stacked spiral inductor exhibiting a Q factor of 5.8, with a pMOS based capacitor of 32% in tuning range, corresponding to 3-4GHz of tuning frequency, is...
This paper presents an adaptive body-biased low-voltage VCO. Despite the 0.5-V supply, the VCO uses coarse digital tuning by employing voltage-boosting technique. In addition, the effect of PVT variations is reduced by adaptive body-biasing technique. The proposed VCO is implemented in 0.18 mum CMOS technology and operates at 2.4 GHz. It achieves phase noise of -115.8 dBc/Hz at 1-MHz offset and 7...
A fully integrated dual-band LC voltage control oscillator designed in a 0.18-mum CMOS technology for 5.8-GHz/2.0-GHz wireless communication applications is described. The frequency band switching is accomplished with switched-inductor technique. The dual-band oscillator can be operated in 5.38~6.23 GHz and 1.78~2.07 GHz with 15% frequency tuning range. Two different inductors are used for the frequency...
This paper presents the design, implementation, and measurement of a novel low flicker noise RF mixer in a 0.18 mum CMOS process for C-band direct conversion receivers. The low flicker noise mixer is implemented by incorporating a double-balanced Gilbert-type configuration, the RF leakage-less current bleeding technique, and Cp resonating technique. By using two separate inductors at the node between...
Design, implementation, and simulation of ultra-low-power LC-VCOs with quadrature signal generation are presented, as well as the analysis and the comparison of several different VCO topologies. The VCO topology having the best performance is then used further for quadrature signal generation. Based on a 0.18mum RF/mixed-signal CMOS process, the VCOs are simulated using 1V supply voltage. It is demonstrated...
Power-saving techniques such as opamp current reuse and capacitive level shift reduce the power consumption of a 10b pipelined ADC to 220muW/MHz. A 50MS/S prototype in 0.18mum CMOS consumes 18mW (11mW for analog) at 1.8V and occupies 1.1times1.3mm2. The measured ENOB of the ADC is 9.2b (8.8b) for a 1MHz (20MHz) input
A 2 GHz differentially tuned CMOS monolithic LC-VCO was designed and fabricated in 0.18-mum CMOS process. The VCO has a 16.15% tuning range (from 1.8998 GHz to 2.2335 GHz) due to a combination of analog and digital tuning technique (4-bit binary switch-capacitor array). The measured phase noise is -118.17 dBc/Hz at 1 MHz offset from 2.158 GHz carrier. With the presented smart switch, the phase noise...
A new frequency synthesizer architecture with low-power and very short settling time is introduced for 2.4GHz ZigBee applications. It uses two-point channel control with divider control and direct VCO control. A DAC with tunable gain is used along with a linearized varactor for the direct VCO control path. Despite the use of an integer-N architecture with 50kHz loop bandwidth, we have achieved a frequency...
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