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A low power full custom Half-Band FIR digtal Alter with fixed coefficients used for sigma-delta ADC is presented. The Half-Band FIR digtal filter uses three- stage cascaded strcture and has linear phase and lowpass characteristics. It achieves passband ripple of 0.003dB and stopband attenuation of 82dB, and dissipates only 15mW with a 3V supply based on a 0.35um CMOS process.
The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to the calibration. We present a 14 bit DAC, designed in a CMOS 0.35 μm process and based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. This DAC features an INL lower than 0.5 LSB at 5 MHz, and dissipates less than 7 mW.
This paper presents a sigma-delta modulator of two-order with switched-capacitors (SC) techniques for low power in 0.18 um CMOS process. Without continues current transmission SC techniques present a discrete low power system. And a low power op amplifier with discrete common-mode feedback and a dynamic comparator is also designed. This new amp works under the supply of 1.8 v and with the direct current...
A 10 bit 165 MS/s pipelined ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. The ADC consumes 56 mW and occupies 0.15 mm2. It is fabricated in a 90 nm 1.2 V CMOS process and achieves 55 dB SNR for a 60 MHz input. A novel measurement technique called ldquopad noise suppressionrdquo is introduced to prevent...
Data retention power gating is a commonly used method for leakage reduction in deep submicron SRAM. However, application of such methods result into reduced stability of the SRAM bitcell. Moreover, reducing supply voltage and increasing process variation put a limitation on such usage in deep submicron processes. Present scheme describes a method to enhance stability while applying such data retention...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
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