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We reported high-speed transport properties on gallium nitride (GaN) single nanowire (NW) transistors laterally grown on the (0001) sapphire substrates. Due to the preservation of surface stoichiometry and passivation effects by the facet growth of [112̅0]Ga2O3/GaN, the 60nm-dia. SNW-MOSFET device of 0.2μm gate length was shown to exhibit a saturation current of 145μA, current on/off ratio of 105,...
In this paper first results on the growth of thin layers of Al2O3, HfO2 and nanolaminates of them, by atomic layer deposition are reported. The electrical characterization of the deposited layers has been carried out by means of the analysis of the capacitance-voltage and current-voltage characteristics of aluminum-high-k dielectric-silicon capacitors. The obtained results show that for the same physical...
An analytical subthreshold surface potential model for Dual Material Gate MOSFET including the effect of inner fringing field is presented, considering surface potential variation with the depth of the channel depletion layer. A pseudo two dimensional method is adopted and a more accurate prediction of surface potential including the fringing field effect is reported.
Organic thin film transistors (OTFT) characteristics generally depend on organic semiconductor thin film growth conditions and the gate dielectric. Authors concerned with the basic properties of pentacene OTFT, where the gate dielectric consists of three different dielectric materials: SiO2 (HMDS treated), SiO2 covered with diacetylene SAM formed by the Langmuir-Blodgett method and SiO2 covered with...
This paper describes about III-V integration on silicon and summarizes the recent progress on the research efforts to combine the merits of III-V and silicon, on the same silicon wafer, for future high-speed and low-power nanoelectronics. The successful integration of III-V on silicon can open up opportunities for integrating new functionalities and features on silicon, such as integrating logic,...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
Drain-induced barrier lowering in substrate-induced strained-Si n-MOSFETs has been investigated. The variation of subthreshold swing as a function of both the gate length and gate to source voltage has also been examined.
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Single, high energy, high LET, ions impacting on a Floating gate array at grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Every time a FG is crossed by a single ion, it experiences a charge loss which permanently degrades the stored information. If the ion crosses more than one FG, the threshold voltage of all those FGs interested by its track...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
This research deals with ZnO flexible active matrix material for display backplanes and integrated circuits. Device fabrication and characterization for enabling high performance displays is demonstrated with their associated integrated circuits on low-cost polymer substrates.
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics...
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