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The AC power supply clocked circuits is a class of digital gates which uses clock signals replacing the VDD and ground terminals in the static gates. In this paper the guideline for an AC-clocked logic gate is described. One crucial problem related to digital circuits design is the zero-order calculation or first guess on the device dimensions. The DCVSL-Differential Cascode Voltage Switching Logic...
This paper presents an energy-efficient processing platform for wearable sensor nodes, designed to support diverse biological signals and algorithms. The platform features a 0.5V-1.0V 16b microcontroller, SRAM, and accelerators for biomedical signal processing. Voltage scaling and block-level power gating allow optimizing energy efficiency under applications of varying complexity. Programmable accelerators...
Differential Power Analysis (DPA) is a powerful Side-Channel Attack (SCA) targeting as well symmetric as asymmetric ciphers. Its principle is based on a statistical treatment of power consumption measurements monitored on an Integrated Circuit (IC) computing cryptographic operations. A lot of works have proposed improvements of the attack, but no one focuses on ordering measurements. Our proposal...
Today power optimization is an important field of research due to the increasing need for less power consumption, dramatic decrease of circuit's MTBF on high temperature and cooling difficulties. It is investigated that only 30% improvement in battery performance will be obtained in five years. This paper is an overview on power estimation and optimization researches and the overall flow of presenting...
Effective implementation and efficient utilization of clock gating logic is a critical element for dynamic power optimization. In this paper we propose three new clock gating effectiveness metrics to assess the quality of clock gating. We then propose applications of these metrics combined with RT level activity profiles, that enable accurate power estimation at downstream physical design stages....
Multi-context reconfigurable arrays provide the ability for fast dynamic reconfiguration once the configurations have been stored into the architecture's context memory. Besides switching the context of the entire array it is also possible to reconfigure contexts from outside the array, which we call external reconfiguration. If supported by the architecture, this reconfiguration, as well as switching...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
The Track-and-Hold Amplifier (THA) practically accounts for most of the dynamic parameters of an ADC and hence optimization of its performance is crucial. This paper presents the design of a bipolar Track- and-Hold Amplifier (THA) capable of operating at 10 Gsamples/s and suitable for use with analogue-to-digital converters with a resolution of up to 8-bits. The high sampling rate prevents the use...
In this paper a method is being proposed to find the optimal dimension of Programmable Gate Macro Block (PGMB) in clock-free nanowire crossbar architecture. A PGMB is a nanowire crossbar matrix with discrete number of rows and columns on which the NCL (Null Convention Logic) gates can be programmed. This method uses inherent redundancy to route through defective crosspoints. A 6 X 10 defect-free crossbar...
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