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Due to process variations at the very low technology nodes, the manufactured chips are grouped into different speed bins. Currently, various types of maximum operation frequency (Fmax) tests are performed for efficient speed binning by applying complex functional or structural test patterns, which incurs high test cost. In this paper, a novel on-chip Binning Sensor is proposed which can monitor the...
As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
We report a system-on-chip (SoC) realised in 130nm CMOS for implantable telemetry systems and mobile health applications featuring 6 neural stimulation channels and acquisition circuits for 9× electrode-based recordings (ExG), 4×/32× photo-plethysmography (PPG), bio-impedance, and temperature. The SoC includes a low-power quad-core processor (34μW/MHz) with sophisticated power and clock management...
A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondingly tuning selected stage and memorizing associated settings. After correcting all individual stages, the total delay of the line is compared with the...
This work presents a fully-integrated sub-GHz radio System on Chip (SoC) for Low-Power Wide-Area Networks (LPWAN) and Internet of Things (IoT) applications. The receiver (RX) achieves 77dB blocker rejection and −106dBm sensitivity at 50kbps. The transmitter (TX) features a Switched-Capacitor Power Amplifier (SCPA) that delivers 13.5dBm output power. To fulfil stringent Japanese emission regulation,...
The LEON series of processors has enabled space missions during the two past decades. This paper discusses the past, present and future of the LEON series of SPARC 32-bit space-grade microprocessors and system-on-chip devices.
An ultra-low power autonomous MPPT algorithm that maximizes the efficiency of a monolithic 0.98 mm2 solar harvester is presented. Using only the pn-junctions of the standard 130 nm single n-well process, the monolithic harvester can serve as supply for wireless sensor grains. Based on the perturbation and observation method, the MPPT algorithm maximizes the output current of the integrated charge...
A novel 2-stage testing structure for CMOS pixel sensor (CPS) is proposed here. The test stimuli are based on applying the electrical pulses instead of light stimuli on photosensitive area, for pure electrical test. The voltage stimuli applied is generated by charge-pump phase locked loop (CP-PLL) which is used here as on-chip clock, exploiting the dual role. Existing charge-pump circuit as stimulator...
A number of critical design decisions, such as network topology, buffer sizes, flow control mechanism and so on so forth, have to be evaluated in any NoC the design. Designs and verifications of NoCs are based on either software simulations, which are extremely slow and inaccurate for complex models, or hardware emulations using low/mid-class FPGAs, where the scalability of the NoC system is intensively...
To achieve a high performance of a system on chip design we should focus on a faster chip communication architecture based on different arbitration scheme. Where all master requests are having different priority. So designing the arbiter having ability to perform in worst corner cases. This paper is introduction to a modified dynamic bus arbiter based on fuzzy logic for a system on chip design architecture...
This paper, formulates a novel technique that explores on-chip IR drop reduction and instantaneous demanded peak-current reduction simultaneously. Proposed solution leverages unused timing slacks, and schedules the clock arrival times to relax the peak current which is delivered through each via-stack in the on-chip IR hot-spots. In addition, this paper formulates and introduces a new evaluation metric...
Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise as technology scales down and power density increases. However, their effectiveness highly depends on the design parameters of the PDN,...
This paper proposes a resilient Time-to-Digital Converter (TDC) that lends itself to cell-based design automation. We adopt a shrinking-based architecture with a number of distinctive techniques. First of all, a specialized on-chip re-calibration scheme is developed so that the real-time transfer function of the TDC in silicon (which maps an input pulse-width to its corresponding output code) can...
A displacement-to-digital converter (DDC) based on inductive (eddy-current) sensor is presented. The sensor is embedded in a self-oscillating front-end, whose 145MHz output is then digitized by a ratiometric ΔΣ ADC. Over a 10μm range, the DDC achieves 1.85nm resolution (1.02 pH), in a 2kHz bandwidth. It draws 9.1mW from a 1.8 V supply making it the most energy-efficient ECS interface ever reported.
A fully integrated buck regulator for ultra-low voltage application is presented featuring (1) an ultra-high switching frequency at 2GHz with small inductor size at low load current and (2) a resonant switching technique rendering significant efficiency improvement. With small on-chip inductors, the test chip shows a wide voltage tuning range of 0.3–0.86V, at 10–40mA low current, up to 73% efficiency...
This paper presents an advanced 2.3–2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load...
A wireless system-on-chip with integrated antenna, power harvesting and biosensors is presented that is small enough, 200µm × 200µm × 100µm, to allow painless injection. Small device size is enabled by: a 13µm × 20µm 1nA current reference; optical clock recovery; low voltage inverting dc-dc to enable use of higher quantum efficiency diodes; on-chip resonant 2.4GHz antenna; and array scanning reader...
We present an integer-N all-digital frequency-locked loop (ADFLL) suitable for dynamic voltage and frequency scaling in system-on-chips targeting mW-consumption. The proposed ADFLL operates with a 32 kHz clock reference, and offers a large clock multiplication factor of 32786, resulting in a wide tuning-range from 19 kHz to 1.048 GHz at 1.2 V and to 250 MHz at 0.8 V,. It incorporates a jitter reduction...
This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm,...
Near-threshold computing is emerging as a promising energy-efficient alternative for power-constrained environments. Unfortunately, aggressive reduction in supply voltage to the near-threshold range, albeit effective, faces a host of challenges. This includes higher relative leakage power and high error rates, particularly in dense SRAM structures such as on-chip caches. This paper presents an architecture...
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