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A Physical Unclonable Function (PUF) is often used to uniquely identify an integrated circuit by extracting its internal random differences using so-called Challenge Response Pairs (CRPs). As CRPs include unique information about the underlying hardware variations, PUF design is a promising approach to provide authentication and IP-protection capabilities. In this paper, an XOR-gate-based configurable...
One of the consequence of the scaling down of latest technologies, is that digital circuits are more prone to be affected by faults caused by physical manufacturing defects, environmental perturbations (e.g., radiations, electromagnetic interference), or aging-related phenomena. Understanding the behavior of the whole system in the presence of faults affecting digital circuits is crucial for designing...
All Programmable System-on-Chip (APSoC) devices can offer high performance because of the combination between high speed embedded processors and the flexibility of the programmable logic. Thus, APSoC can be attractive for the European Organization for Nuclear Research (CERN) environment, which hosts the Large Hadron Collider (LHC), due to the large amount of equipment and instrumentation electronics...
High-Level Synthesis (HLS) has opened an opportunity for software programmers to target FPGA more rapidly. When developing HLS tools, tests are desirable to ensure their function, reliability and performance. When modifications are applied to a tool, Non- Regression Test (NRT) asserts that the changes have intended effect while Regression Test (RT) verifies that the tool still performs correctly without...
According to the development status of reconfigurable computing specially its applications and advantages in the domain of aviation and spaceflight, this paper makes a research in the availability of reconfigurable computing. Through three aspects, reconfigurable chip, development tool and compilation technology, this paper analyses the obstacles reconfigurable computing faced with. In the end, this...
Solid State Disk (SSD) storage systems are the storage medium of choice in modern embedded devices, and so the performance, lifespan, and reliability of these devices is an increasing issue in many application domains. Previous work has proposed adaptations to RAID architectures to render them suitable for SSD systems. However these solutions open a number of challenges such as wear-levelling across...
Punjabi is ranked 1st in languages of Pakistan [5], 11th in Indian languages [6] and 3rd in Indian Subcontinent. In order to write Punjabi: Gurmukhi script is used in India and Shahmukhi in Pakistan. A lot of research is going on in Pakistan and India in the domain of natural language processing but, no research group is working especially for Punjabi to design Unicode reader. The Unicode range of...
The very high levels of integration and submicron device sizes used in emerging VLSI systems and FPGAs lead to frequent occurrences of defects and operational faults. Thus, the need for fault tolerance and reliability of deployed systems becomes increasingly prominent. This paper discusses fault tolerance and reliability observed in the design of a parallel self-healing VLSI system, based on partial...
Physical Unclonable Functions (PUFs) provide secure cryptographic keys for resource constrained embedded systems without secure storage. A PUF measures internal manufacturing variations to create a unique, but noisy secret inside a device. Syndrome coding schemes create and store helper data about the structure of a specific PUF to correct errors within subsequent PUF measurements and generate a reliable...
This paper presents an implementation of a low complexity Wavelet OFDM system based on Haar function. The OFDM transmitter generates the orthogonal signals, and the OFDM receiver detects the signals. The idea of low complexity is the arrangement and the multistage calculations of coefficients. It was shown that the number of multiplier and adder was reduced. Hardware model presented is scalable to...
Today system reliability, availability, serviceability, and manageability (RASM) are becoming more crucial as computer based systems continue to increase in complexity and importance to our daily lives. Redundancy is a viable approach to improve the RASM attributes of a system. There are many forms of fault tolerant/redundant system architectures employed in both commercial and military /aerospace...
In this paper we presents the design of a very low power and high throughput AES processor. A sophisticated AES algorithm without sacrificing its security features, throughput and area is used to design the processor. Due to the optimization of the algorithm and a number of design considerations, the processor shows its superiority over other AES processors. The proposed processor is simulated on...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
As semiconductor technology approaches the atomic scale, electronic systems are increasingly burdened by physical variations and uncertainty. Traditionally-designed systems lack an ability to adapt to these fine-grained effects and are thus becoming more inefficient, error-prone, and subject to early wear out. This paper describes the paradigm of physically-adaptive computing (PAC), in which systems...
Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of...
This paper introduces the principle of AES algorithm and the detailed description and implementation on FPGA. This system aims at reduced hardware structure. Compared with the pipeline structure, it has less hardware resources and high cost-effective. And this system has high security and reliability. This AES system can be widely used in the terminal equipments.
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against...
The paper realizes a design of digital fuzzy adaptive tuning PID electronic governor. It is based on VHDL description and implemented on FPGA. The paper proposes to detect the speed with duty cycle calculation and use fuzzy-control rules to amend the PID parameters on line to achieve the fuzzy adaptive tuning PID control. On this basis, the paper introduces the implementation of the system in detail,...
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