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This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference...
In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed-forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub-filters. Timing multiplexing and resource reuse methodology...
This paper presents a dual sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals more efficiently and proposes an 11b switched-capacitor pipeline ADC based on this technique. With the dual sampling technique, the input signal power of the ADC can be boosted without getting excessive clipping noise and the ADC can have a higher resolution over the critical low...
A low power, high resolution two-step hybrid delta-sigma/pipelined modulator (HDSP) is presented. The feedback architecture of the HDSP modulator is modified to allow higher orders of noise shaping. The pipelined quantizer is simplified. Finally, the input signal range of the HDSP modulator is extended beyond the supply voltage. The prototype chip is implemented in a 0.18/im CMOS process. With a 1...
A new low-power switched-capacitor integrator is proposed for high-resolution ΔΣ ADCs. Compared to the conventional switched-capacitor integrator, it achieves much lower power dissipation for the same noise specifications. To verify the effectiveness of the new integrator, and to compare it with the conventional one, a third-order delta-sigma modulator was simulated. A detailed comparison between...
A single-loop delta-sigma modulator based on path-coupling and double-sampling is proposed. This modulator employs a noise-shaped integrating quantizer which by itself increases the order of noise shaping by one. The integrating quantizer used in this structure holds its quantization error at the end of the evaluation phase, and hence this voltage is available in purely analog form and eliminates...
This paper presents a new two-stage cascade ΣΔ modulator architecture that uses inter-stage resonation to increase its effective resolution as compared to conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combination of these two strategies, together with the use of unity signal transfer function in all stages, make the presented modulator highly...
A 3 GHz wideband SigmaDelta fractional-N synthesizer with an exponential settling voltage-mode PFD is presented. The 1 MHz band-width type-I PLL loop utilizes the exponential small-signal settling characteristics of a voltage-mode NMOS (follower) LDO based PFD-CP to reduce in-band quantization noise leakage by more than 13 dB without the need for a noise suppression DAC. The PLL is fabricated on a...
In this paper several techniques are presented to significantly relax the analog circuit requirements such as the amplifiers dc gain and capacitors matching of multi-stage noise-shaping (MASH) sigma-delta modulators. In the first technique, one order redundant noise shaping is employed in the early stages and the first order shaped quantization error of the early stages is used as the input of the...
This paper investigates and resolves in-channel/quadrature channel (I/Q) imbalances in quadrature band pass delta sigma modulators. These mismatches result in image interference and noise being aliased into the desired signal band, thus degrading the dynamic range of the modulators. A novel dynamic element match shaping scheme is proposed to cancel the aliasing of image interference, noise, and self-image...
We describe an in-situ analog technique for estimating time constant shifts in continuous-time single bit delta-sigma modulators. We show that the variance of the first integrator output of the modulator's loop filter is a good indicator of RC time constants. The nominal values of the time constants are restored by digitally controlling the resistance and capacitance values (realized as switched banks)...
In this paper, a technique is proposed to suppress the fractional spur induced by non-linearity of the loop in all digital PLLs (ADPLLs). The measurement results show that the fractional spurs are reduced by at least 9 dB, to below -75 dBc, when the technique is applied to a conventional all digital PLL (ADPLL) at 3.6 GHz. The extra silicon area needed for technique is only 0.02 mm2.
A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. It provides 81 dB SNDR, 82 dB dynamic range, and -98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 V power supply (analog power 4.4 mW, digital power 3.7 mW). Its figure-of-merit is among the best...
This paper presents the possibility of employing non-linear low-resolution DACs in the feedback paths of multi-bit second-order Sigma-Delta modulators. The proposed technique is particularly attractive in applications such as hearing aids, requiring a very large dynamic range and medium signal-to-noise-plus-distortion-ratio. As demonstrated through simulated results in which noise and mismatch effects...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
This paper describes a sigma delta switched capacitor CMOS ADC using multi-bit quantization and feedback path for minimum power consumption. Multi-bit quantization has up to now been avoided because the linearity of the DAC in the feedback path directly limits the linearity of the whole converter. By using data weighted averaging, the non-linearity error related to the mismatch of the DAC components...
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