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This work demonstrates a fully integrated 24 GHz CMOS receiver for high gain and wireless sensor network. The receiver incorporates a low noise amplifier, double-balanced mixer and an active balun for single to differential. This mixer designs with active load to decrease power dissipation. To increase mixer gain, an inductor is added to eliminate parasitic capacitances at the load of input transistor...
This paper presents a 0.5-3.5GHz wideband CMOS low noise amplifier (LNA) for LTE application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback that is used to do input matching and reduce the noise figure. Source follower and LC series resonances are used to do output matching. The LNA achieves the gain of 17dB ∼ 22dB, a noise figure (NF) of 2.23 ∼ 2.68 dB...
In this paper we present extremely small size integrated balun topologies in 65 nm CMOS technology for millimeter wave applications. An octagon stacked version of the transformer balun and respectively, a stacked version of the Marchand balun are proposed. Both balun structures are designed for 60 GHz applications and present a wideband performance, satisfactory phase and amplitude imbalances. The...
The impact of the emitter polysilicon etching in Tetramethyl Ammonium Hydroxide (TMAH) on the characteristics of high-linearity mixers fabricated with the low-cost Horizontal Current Bipolar Transistor (HCBT) is analyzed. During emitter formation, the thick layer of α-Si is deposited over the whole wafer, which is then etched-back in the TMAH. The emitter thickness depends on the TMAH etching time...
This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and employs one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns...
This paper presents a design of 60-GHz exponential tapered slot Vivaldi antenna-on-chip (AOC). The antenna is designed using standard 0.18µm six metal-layers CMOS technology. A double-Y balun feeding structure is used to make transition from coplanar waveguide to slot-line. Two techniques are investigated for improving antenna radiation properties. The first technique incorporates equal corrugations...
This paper presents the design and implementation of an integrated wideband Marchand balun in standard 65nm CMOS technology. The proposed balun operates from 16 GHz to 21 GHz achieving high coupling together with significantly low phase and amplitude imbalance between the balun outputs. A new balun structure is proposed to solve the nonideal ground problem in CMOS-based microwave circuits, and coherently...
This paper presents a novel unbalanced transformerless vector-sum phase shifter architecture. The proposed approach is based on the forming of four signals from the input unbalanced signal by an RC quadrature all-pass filter. These signals are subtracted to obtain a pair of orthogonal signals which are added on the load network of the Gilbert cells with weighted coefficients to form the differential...
This paper presents the simulation results of a linear, fully integrated, two-stage digitally programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is composed of a set of amplifying cells which can be enabled or disabled independently by a digital control circuit. All seven operational modes are univocal in terms of 1 dB output compression point (OCP1dB), saturated output...
In this paper two main approaches to the realization of vector-modulation phase shifters quadrature formers based on RC and RLC structures are considered for the case of microwave 180 nm CMOS technology. The choice of unbalanced input structure is explained due to CMOS balun characteristics. Phase and amplitude errors are compared, as well as input matching. In conclusion, main advantages and disadvantages...
This paper is enunciated a LNA with high gain and minimum noise performance for Global Positioning System (GPS) application. The CMOS Low Noise amplifier implementation is designed and simulated via cadence using UMC 90 nm library. The topology is single ended LNAs designed which uses cascaded transistor for isolation; the common source transistor is driven by common gate transistor. To have objective...
The vast unallocated frequency band lying above 275GHz offers enormous potential for ultrahigh-speed wireless communication. An overall bandwidth that could be allocated for multi-channel communication can easily be several times the 60GHz unlicensed bandwidth of 9GHz. We present a 300GHz transmitter (TX) in 40nm CMOS, capable of 32-quadrature amplitude modulation (QAM) 17.5Gb/s/ch signal transmission...
A fully-integrated ultra-wideband power amplifier (PA) for multi-mode multi-band applications is designed and implemented in a standard 0.25 μm Ultra-CMOS Silicon-on-Sapphire (SOS) technology. The PA consists of two series stacked Cascode configuration to achieve high output power while maintaining stability. The PA utilizes stacked transistor switches at the input to extend the operation bandwidth...
This paper presents a 6-bit phase shifter with a low root-mean-square (RMS) phase error and a flat gain across 1.9–2.6GHz. An input balun which utilizes a differential signal correction system consisting of two capacitor-cross-coupled (CCC) pairs and one CCC buffer is realized to ensure good phase and amplitude balance. Based on the relationship of the W/L of DAC cells, an encode rule which makes...
In this paper, we present a low power consumption and high gain low noise amplifier using transformer feedback to neutralize the gate-source and gate-drain overlap capacitance of a FET. It is a single-ended amplifier designed in 65nm CMOS technology for 60 GHz transceiver. This LNA achieves a simulated gain of 10.64 dB, noise figure of 3.10 dB at 60 GHz.
A Narrowband Differential Low Noise Amplifier (DLNA), applicable for Global Positioning System receivers, with center frequency of 4.1GHz and Bandwidth of 90MHz using 180nm rf CMOS process parameters is designed in this paper. Rigorous optimization is carried out for the following parameters-Input and Output Impedance Matching, Gain, Bandwidth, Noise Figure, Power Consumption, 1dB Compression Point,...
This paper presents the design and simulation of an inductive degeneration low noise amplifier (LNA) for impulsionel radio ultra wide band receiver for biomedical implant. Several techniques was used in this study to improve the LNA features for the [1,5]GHz frequency band. The most important are the use of the diode connected load, the degeneration source and the cascode design. A fully integrated...
Integrated circuit researches in KAIST in the area of digital polar CMOS power amplifiers (DPAs) are presented, which include a high dynamic range DPA, and a dual-power-mode output matching network for a DPA to improve low power efficiency. The high dynamic range DPA introduces the sub-amplifier cell array with LO leakage canceller to improve local oscillator (LO) leakage and a digitally controlled...
This paper presents the design and measurements of a 216GHz, 0.5mW transmitter using 65nm bulk CMOS process. The transmitter is formed of an amplifier-multiplier chain, where the power amplifier delivers a Psat =16dBm at 110GHz to a passive frequency doubler. The PA stage employs a novel single-ended to 2-way differential power combiner based on vertically coupled transmission lines. A passive frequency...
A two-stage mm-wave power amplifier (PA) is presented. Designed in a 65 nm CMOS process, the PA employs capacitive neutralization in each stage for increased differential isolation and gain. Baluns are used for single-ended input/output signal to balanced signal conversion, and the interstage matching consists of a 2:1 transformer. With a 1.2 V supply, at 67 GHz, measurements show a gain of 16.8 dB,...
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