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In this paper, we present a method for creating LDPC codes which are specifically designed to be hardware friendly. Our method involves constraining the cyclic shift values in the base H-matrix to reduce the complexity of the cyclic shift hardware. We show that the decoder hardware implementation for these codes has higher throughput and lower power consumption than decoders designed for traditional...
With the rapid development of deep submicron (DSM) VLSI circuit design, many issues such as time closure and power consumption are making the physical design more and more challenging. This paper proposes a method aiding in low clock skew which is applicable to the clock tree synthesis (CTS) design flow. The method works by breaking up the original clock root into several pseudo clock sources at the...
In this paper the effects of multiplier architecture on the overall performance of the OFDM De-modulator for an UWB system are studied. The two commonly used VLSI multiplication algorithms, namely, the Baugh-Wooley algorithm and the Modified-Booth algorithm, are the candidates for this study. Partial product accumulation session can be found in both algorithms. There are two major classes of partial...
This paper describes the low-power design of a MOS current-mode logarithmic adder. The adder utilizes the Brent-Kung tree structure. The design strategy adopted is very simple and effective. Moreover, it can be utilized also for other types of logarithmic adders. To validate it, several adders were designed in a TSMC CMOS 130 nm technology. Results of simulations indicate that the proposed methodology...
This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. Further, we present a design methodology of hybrid carry lookahead/carry skip adders (CLSKAs). This modified carry skip adder is modeled by using both fix and variable block size. In conventional carry skip adder, each block...
IEEE 802.16e standard currently supports mobile subscriber stations, which substantiates the need for energy-efficient communication. In this paper we analyze a novel sleep mode mechanism to be considered for the future IEEE 802.16m standard. We study the overall message delay in the downlink channel and explicitly account for the sleep mode power consumption. Simple expressions are given based on...
Power consumption is an important issue in nanoscale circuits. The multiple supply voltages (MSV) technique, where non-critical parts are supplied with the lower supply voltage, can be used to balance power and performance, as both dynamic and leakage power are reduced with the lower supply voltage. However, level converting circuits must be inserted between different voltage domains to avoid leakage...
In this paper, an asynchronous high-speed logic circuitry using low temperature poly silicon-thin film transistor (LTPS-TFT) and the bootstrapped technology (BST) for liquid crystal display (LCD) is proposed. The proposed logic circuit operates at high frequency region owing to the deep non-saturation operation by using the bootstrapped technology. To confirm some characteristics of the proposed circuit,...
This paper proposes a high energy-efficient pulsed-current-mode transmission line interconnect (PTLI) for on-chip networks. The stacked-switch transmitter (Tx) is introduced for saving a static power of Tx. Point-to-point and multi-drop PTLIs are demonstrated, and simulation results show that the 5-mm-long PTLI with six Txs and six receivers (Rxs) can achieve multi-drop signaling. The point-to-point...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In this paper a hold-friendly scan flip-flop is introduced whose scan pin hold characteristic has improved while data pin timing and power are left intact. This characteristic helps to resolve scan chain hold problem while meeting the maximum frequency in data path. This solution can reduce the number of buffers inserted in the scan chain to fix hold violations. The new flip-flop can save up to 27%...
Sink mobility has become an increasingly important requirement of various sensor network applications. Handling such mobile sink conditions brings new challenges to large-scale sensor networking. This investigation proposed a hybrid-structure routing protocol (HSRP) that combines the benefits of grid-based and cluster-based structures. Grid-based structure is designed to solve the cluster head selection...
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